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Commit 022d3093 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin Committed by Mika Kuoppala
Browse files

drm/i915/icl: Prepare for more rings 



Gen11 will add more VCS and VECS rings so prepare the
infrastructure to support that.

Bspec: 7021

v2: Rebase.
v3: Rebase.
v4: Rebase.
v5: Rebase.
v6:
  - Update for POR changes. (Daniele Ceraolo Spurio)
  - Add provisional guc engine ids - to be checked and confirmed.
v7:
  - Rebased.
  - Added the new ring masks.
  - Added the new HW ids.
v8:
  - Introduce I915_MAX_VCS/VECS to avoid magic numbers (Michal)

v9: increase MAX_ENGINE_INSTANCE to 3

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180228101153.7224-1-mika.kuoppala@linux.intel.com
parent bba73071

drivers/gpu/drm/i915/i915_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -2746,6 +2746,9 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define BLT_RING	ENGINE_MASK(BCS)

#define VEBOX_RING	ENGINE_MASK(VECS)

#define BSD2_RING	ENGINE_MASK(VCS2)

#define BSD3_RING	ENGINE_MASK(VCS3)

#define BSD4_RING	ENGINE_MASK(VCS4)

#define VEBOX2_RING	ENGINE_MASK(VECS2)

#define ALL_ENGINES	(~0)



#define HAS_ENGINE(dev_priv, id) \

drivers/gpu/drm/i915/i915_gem.h

+1 −1
Original line number Diff line number Diff line
@@ -57,6 +57,6 @@ 
#define GEM_TRACE(...) do { } while (0)

#endif



#define I915_NUM_ENGINES 5

#define I915_NUM_ENGINES 8



#endif /* __I915_GEM_H__ */

drivers/gpu/drm/i915/i915_reg.h

+4 −1
Original line number Diff line number Diff line
@@ -178,6 +178,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define BCS_HW		2

#define VECS_HW		3

#define VCS2_HW		4

#define VCS3_HW		6

#define VCS4_HW		7

#define VECS2_HW	12



/* Engine class */
@@ -188,7 +191,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define OTHER_CLASS		4

#define MAX_ENGINE_CLASS	4



#define MAX_ENGINE_INSTANCE    1

#define MAX_ENGINE_INSTANCE    3



/* PCI config space */

drivers/gpu/drm/i915/intel_device_info.c

+3 −0
Original line number Diff line number Diff line
@@ -542,6 +542,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info) 
		info->num_scalers[PIPE_C] = 1;

	}



	BUILD_BUG_ON(I915_NUM_ENGINES >

		     sizeof(intel_ring_mask_t) * BITS_PER_BYTE);



	/*

	 * Skylake and Broxton currently don't expose the topmost plane as its

	 * use is exclusive with the legacy cursor and we only want to expose

drivers/gpu/drm/i915/intel_device_info.h

+3 −1
Original line number Diff line number Diff line
@@ -125,6 +125,8 @@ struct sseu_dev_info { 
	u8 has_eu_pg:1;

};



typedef u8 intel_ring_mask_t;



struct intel_device_info {

	u16 device_id;

	u16 gen_mask;
@@ -132,7 +134,7 @@ struct intel_device_info { 
	u8 gen;

	u8 gt; /* GT number, 0 if undefined */

	u8 num_rings;

	u8 ring_mask; /* Rings supported by the HW */

	intel_ring_mask_t ring_mask; /* Rings supported by the HW */



	enum intel_platform platform;

	u32 platform_mask;