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Commit 01e0d603 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'ntb-4.10' of git://github.com/jonmason/ntb 

Pull NTB update from Jon Mason:

 - NTB bug fixes for removing an unnecessary call to ntb_peer_spad_read,
   and correcting a free_irq inconsistency

 - add Intel SKX support

 - change the AMD NTB maintainer, and fix some bugs present there

* tag 'ntb-4.10' of git://github.com/jonmason/ntb:
  ntb_transport: Remove unnecessary call to ntb_peer_spad_read
  NTB: Fix 'request_irq()' and 'free_irq()' inconsistancy
  ntb: fix SKX NTB config space size register offsets
  NTB: correct ntb_peer_spad_read for case when callback is not supplied.
  MAINTAINERS: Change in maintainer for AMD NTB
  ntb_transport: Limit memory windows based on available, scratchpads
  NTB: Register and offset values fix for memory window
  NTB: add support for hotplug feature
  ntb: Adding Skylake Xeon NTB support
parents 6ac3bb16 dfb7d24c

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -8828,7 +8828,7 @@ T: git git://github.com/jonmason/ntb.git 
F:	drivers/ntb/hw/intel/



NTB AMD DRIVER

M:	Xiangliang Yu <Xiangliang.Yu@amd.com>

M:	Shyam Sundar S K <Shyam-sundar.S-k@amd.com>

L:	linux-ntb@googlegroups.com

S:	Supported

F:	drivers/ntb/hw/amd/

drivers/ntb/hw/amd/ntb_hw_amd.c

+13 −12
Original line number Diff line number Diff line
@@ -138,11 +138,11 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx, 
	base_addr = pci_resource_start(ndev->ntb.pdev, bar);



	if (bar != 1) {

		xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 3);

		limit_reg = AMD_BAR23LMT_OFFSET + ((bar - 2) << 3);

		xlat_reg = AMD_BAR23XLAT_OFFSET + ((bar - 2) << 2);

		limit_reg = AMD_BAR23LMT_OFFSET + ((bar - 2) << 2);



		/* Set the limit if supported */

		limit = base_addr + size;

		limit = size;



		/* set and verify setting the translation address */

		write64(addr, peer_mmio + xlat_reg);
@@ -164,14 +164,8 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int idx, 
		xlat_reg = AMD_BAR1XLAT_OFFSET;

		limit_reg = AMD_BAR1LMT_OFFSET;



		/* split bar addr range must all be 32 bit */

		if (addr & (~0ull << 32))

			return -EINVAL;

		if ((addr + size) & (~0ull << 32))

			return -EINVAL;



		/* Set the limit if supported */

		limit = base_addr + size;

		limit = size;



		/* set and verify setting the translation address */

		write64(addr, peer_mmio + xlat_reg);
@@ -199,6 +193,11 @@ static int amd_link_is_up(struct amd_ntb_dev *ndev) 
	if (!ndev->peer_sta)

		return NTB_LNK_STA_ACTIVE(ndev->cntl_sta);



	if (ndev->peer_sta & AMD_LINK_UP_EVENT) {

		ndev->peer_sta = 0;

		return 1;

	}



	/* If peer_sta is reset or D0 event, the ISR has

	 * started a timer to check link status of hardware.

	 * So here just clear status bit. And if peer_sta is
@@ -207,7 +206,7 @@ static int amd_link_is_up(struct amd_ntb_dev *ndev) 
	 */

	if (ndev->peer_sta & AMD_PEER_RESET_EVENT)

		ndev->peer_sta &= ~AMD_PEER_RESET_EVENT;

	else if (ndev->peer_sta & AMD_PEER_D0_EVENT)

	else if (ndev->peer_sta & (AMD_PEER_D0_EVENT | AMD_LINK_DOWN_EVENT))

		ndev->peer_sta = 0;



	return 0;
@@ -491,6 +490,8 @@ static void amd_handle_event(struct amd_ntb_dev *ndev, int vec) 
		break;

	case AMD_PEER_D3_EVENT:

	case AMD_PEER_PMETO_EVENT:

	case AMD_LINK_UP_EVENT:

	case AMD_LINK_DOWN_EVENT:

		amd_ack_smu(ndev, status);



		/* link down */
@@ -598,7 +599,7 @@ static int ndev_init_isr(struct amd_ntb_dev *ndev, 


err_msix_request:

	while (i-- > 0)

		free_irq(ndev->msix[i].vector, ndev);

		free_irq(ndev->msix[i].vector, &ndev->vec[i]);

	pci_disable_msix(pdev);

err_msix_enable:

	kfree(ndev->msix);

drivers/ntb/hw/amd/ntb_hw_amd.h

+4 −1
Original line number Diff line number Diff line
@@ -148,9 +148,12 @@ enum { 
	AMD_PEER_D3_EVENT	= BIT(2),

	AMD_PEER_PMETO_EVENT	= BIT(3),

	AMD_PEER_D0_EVENT	= BIT(4),

	AMD_LINK_UP_EVENT	= BIT(5),

	AMD_LINK_DOWN_EVENT	= BIT(6),

	AMD_EVENT_INTMASK	= (AMD_PEER_FLUSH_EVENT |

				AMD_PEER_RESET_EVENT | AMD_PEER_D3_EVENT |

				AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT),

				AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT |

				AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT),



	AMD_PMESTAT_OFFSET	= 0x480,

	AMD_PMSGTRIG_OFFSET	= 0x490,

drivers/ntb/hw/intel/ntb_hw_intel.c

+656 −6

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drivers/ntb/hw/intel/ntb_hw_intel.h

+48 −0

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