Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 01dd2fbf authored by Matt LaPlante's avatar Matt LaPlante Committed by Adrian Bunk
Browse files

typo fixes



Most of these fixes were already submitted for old kernel versions, and were
approved, but for some reason they never made it into the releases.

Because this is a consolidation of a couple old missed patches, it touches both
Kconfigs and documentation texts.

Signed-off-by: default avatarMatt LaPlante <kernel1@cyberdogtech.com>
Acked-by: default avatarRandy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: default avatarAdrian Bunk <bunk@kernel.org>
parent 0f035b8e
Loading
Loading
Loading
Loading
+9 −9
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ Introduction
------------

   The kernel provides an interface to manage DMA transfers
   using the DMA channels in the cpu, so that the central
   using the DMA channels in the CPU, so that the central
   duty of managing channel mappings, and programming the
   channel generators is in one place.

@@ -17,24 +17,24 @@ DMA Channel Ordering
   channels to all sources, which means that some devices
   have a restricted number of channels that can be used.

   To allow flexibilty for each cpu type and board, the
   dma code can be given an dma ordering structure which
   To allow flexibility for each CPU type and board, the
   DMA code can be given a DMA ordering structure which
   allows the order of channel search to be specified, as
   well as allowing the prohibition of certain claims.

   struct s3c24xx_dma_order has a list of channels, and
   each channel within has a slot for a list of dma
   channel numbers. The slots are searched in order, for
   the presence of a dma channel number with DMA_CH_VALID
   orred in.
   each channel within has a slot for a list of DMA
   channel numbers. The slots are searched in order for
   the presence of a DMA channel number with DMA_CH_VALID
   or-ed in.

   If the order has the flag DMA_CH_NEVER set, then after
   checking the channel list, the system will return no
   found channel, thus denying the request.

   A board support file can call s3c24xx_dma_order_set()
   to register an complete ordering set. The routine will
   copy the data, so the original can be discared with
   to register a complete ordering set. The routine will
   copy the data, so the original can be discarded with
   __initdata.


+1 −1
Original line number Diff line number Diff line
@@ -2188,7 +2188,7 @@ Your cooperation is appreciated.

136-143 char	Unix98 PTY slaves
		  0 = /dev/pts/0	First Unix98 pseudo-TTY
		  1 = /dev/pts/1	Second Unix98 pesudo-TTY
		  1 = /dev/pts/1	Second Unix98 pseudo-TTY
		    ...

		These device nodes are automatically generated with
+2 −2
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ braindamaged document, if it's finally working, well, it's working.

For one reason or another, low level drivers don't receive as much
attention or testing as core code, and bugs on driver detach or
initilaization failure doesn't happen often enough to be noticeable.
initialization failure don't happen often enough to be noticeable.
Init failure path is worse because it's much less travelled while
needs to handle multiple entry points.

@@ -160,7 +160,7 @@ resources on failure. For example,
  devres_release_group(dev, NULL);
  return err_code;

As resource acquision failure usually means probe failure, constructs
As resource acquisition failure usually means probe failure, constructs
like above are usually useful in midlayer driver (e.g. libata core
layer) where interface function shouldn't have side effect on failure.
For LLDs, just returning error code suffices in most cases.
+2 −2
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ Deferred IO

Deferred IO is a way to delay and repurpose IO. It uses host memory as a
buffer and the MMU pagefault as a pretrigger for when to perform the device
IO. The following example may be a useful explaination of how one such setup
IO. The following example may be a useful explanation of how one such setup
works:

- userspace app like Xfbdev mmaps framebuffer
@@ -28,7 +28,7 @@ a relatively more expensive operation.

For some types of nonvolatile high latency displays, the desired image is
the final image rather than the intermediate stages which is why it's okay
to not update for each write that is occuring.
to not update for each write that is occurring.

It may be the case that this is useful in other scenarios as well. Paul Mundt
has mentioned a case where it is beneficial to use the page count to decide
+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ OPTIONS
  aname=name	aname specifies the file tree to access when the server is
  		offering several exported file systems.

  cache=mode	specifies a cacheing policy.  By default, no caches are used.
  cache=mode	specifies a caching policy.  By default, no caches are used.
			loose = no attempts are made at consistency,
                                intended for exclusive, read-only mounts

Loading