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Commit 00bd16f2 authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Chris Wilson
Browse files

drm/i915/guc: Remove action status and statistics from debugfs 



Usefulness of these stats was over-advertised.

v2: remove duplicated engine stats (Chris)

Suggested-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170515170610.35528-1-michal.wajdeczko@intel.com


Acked-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 2c80353f

drivers/gpu/drm/i915/i915_debugfs.c

+0 −19
Original line number Diff line number Diff line
@@ -2512,9 +2512,6 @@ static int i915_guc_info(struct seq_file *m, void *data) 
{

	struct drm_i915_private *dev_priv = node_to_i915(m->private);

	const struct intel_guc *guc = &dev_priv->guc;

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	u64 total;



	if (!check_guc_submission(m))

		return 0;
@@ -2523,22 +2520,6 @@ static int i915_guc_info(struct seq_file *m, void *data) 
	seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);

	seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);



	seq_printf(m, "GuC total action count: %llu\n", guc->action_count);

	seq_printf(m, "GuC action failure count: %u\n", guc->action_fail);

	seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd);

	seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status);

	seq_printf(m, "GuC last action error code: %d\n", guc->action_err);



	total = 0;

	seq_printf(m, "\nGuC submissions:\n");

	for_each_engine(engine, dev_priv, id) {

		u64 submissions = guc->submissions[id];

		total += submissions;

		seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",

			engine->name, submissions, guc->last_seqno[id]);

	}

	seq_printf(m, "\t%s: %llu\n", "Total", total);



	seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);

	i915_guc_client_info(m, dev_priv, guc->execbuf_client);

drivers/gpu/drm/i915/i915_guc_submission.c

+0 −3
Original line number Diff line number Diff line
@@ -615,9 +615,6 @@ static void __i915_guc_submit(struct drm_i915_gem_request *rq) 


	client->submissions[engine_id] += 1;



	guc->submissions[engine_id] += 1;

	guc->last_seqno[engine_id] = rq->global_seqno;



	spin_unlock_irqrestore(&client->wq_lock, flags);

}

drivers/gpu/drm/i915/intel_uc.c

+0 −7
Original line number Diff line number Diff line
@@ -440,9 +440,6 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len) 
	mutex_lock(&guc->send_mutex);

	intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);



	dev_priv->guc.action_count += 1;

	dev_priv->guc.action_cmd = action[0];



	for (i = 0; i < len; i++)

		I915_WRITE(guc_send_reg(guc, i), action[i]);
@@ -471,11 +468,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len) 
		DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"

			 " ret=%d status=0x%08X response=0x%08X\n",

			 action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));



		dev_priv->guc.action_fail += 1;

		dev_priv->guc.action_err = ret;

	}

	dev_priv->guc.action_status = status;



	intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);

	mutex_unlock(&guc->send_mutex);

drivers/gpu/drm/i915/intel_uc.h

+0 −10
Original line number Diff line number Diff line
@@ -187,16 +187,6 @@ struct intel_guc { 
	DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);

	uint32_t db_cacheline;		/* Cyclic counter mod pagesize	*/



	/* Action status & statistics */

	uint64_t action_count;		/* Total commands issued	*/

	uint32_t action_cmd;		/* Last command word		*/

	uint32_t action_status;		/* Last return status		*/

	uint32_t action_fail;		/* Total number of failures	*/

	int32_t action_err;		/* Last error code		*/



	uint64_t submissions[I915_NUM_ENGINES];

	uint32_t last_seqno[I915_NUM_ENGINES];



	/* GuC's FW specific registers used in MMIO send */

	struct {

		u32 base;