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Commit 000a830e authored by Alex Estrin's avatar Alex Estrin Committed by Doug Ledford
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IB/rdmavt: Post receive for QP in ERR state 



Accordingly IB Spec post WR to receive queue must
complete with error if QP is in Error state.
Please refer to C10-42, C10-97.2.1

Reviewed-by: default avatarMike Marciniszyn <mike.marciniszyn@intel.com>
Reviewed-by: default avatarDennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: default avatarAlex Estrin <alex.estrin@intel.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent d0e859c3

drivers/infiniband/sw/rdmavt/qp.c

+24 −9
Original line number Diff line number Diff line
@@ -1364,6 +1364,8 @@ int rvt_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 
	struct rvt_qp *qp = ibqp_to_rvtqp(ibqp);

	struct rvt_rwq *wq = qp->r_rq.wq;

	unsigned long flags;

	int qp_err_flush = (ib_rvt_state_ops[qp->state] & RVT_FLUSH_RECV) &&

				!qp->ibqp.srq;



	/* Check that state is OK to post receive. */

	if (!(ib_rvt_state_ops[qp->state] & RVT_POST_RECV_OK) || !wq) {
@@ -1390,15 +1392,28 @@ int rvt_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, 
			*bad_wr = wr;

			return -ENOMEM;

		}

		if (unlikely(qp_err_flush)) {

			struct ib_wc wc;



			memset(&wc, 0, sizeof(wc));

			wc.qp = &qp->ibqp;

			wc.opcode = IB_WC_RECV;

			wc.wr_id = wr->wr_id;

			wc.status = IB_WC_WR_FLUSH_ERR;

			rvt_cq_enter(ibcq_to_rvtcq(qp->ibqp.recv_cq), &wc, 1);

		} else {

			wqe = rvt_get_rwqe_ptr(&qp->r_rq, wq->head);

			wqe->wr_id = wr->wr_id;

			wqe->num_sge = wr->num_sge;

			for (i = 0; i < wr->num_sge; i++)

				wqe->sg_list[i] = wr->sg_list[i];

		/* Make sure queue entry is written before the head index. */

			/*

			 * Make sure queue entry is written

			 * before the head index.

			 */

			smp_wmb();

			wq->head = next;

		}

		spin_unlock_irqrestore(&qp->r_rq.lock, flags);

	}

	return 0;