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Commit ffac0e96 authored by Zumeng Chen's avatar Zumeng Chen Committed by David S. Miller
Browse files

net: macb: ensure ordering write to re-enable RX smoothly 



When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:

<write ~MACB_BIT(RE)>
+ wmb();
<write MACB_BIT(RE)>

There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.

Signed-off-by: default avatarZumeng Chen <zumeng.chen@windriver.com>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a0b44eea

drivers/net/ethernet/cadence/macb.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -1157,6 +1157,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id) 
		if (status & MACB_BIT(RXUBR)) {

		if (status & MACB_BIT(RXUBR)) {

			ctrl = macb_readl(bp, NCR);

			ctrl = macb_readl(bp, NCR);

			macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));

			macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));

			wmb();

			macb_writel(bp, NCR, ctrl | MACB_BIT(RE));

			macb_writel(bp, NCR, ctrl | MACB_BIT(RE));





			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)

			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
@@ -2769,6 +2770,7 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id) 
	if (intstatus & MACB_BIT(RXUBR)) {

	if (intstatus & MACB_BIT(RXUBR)) {

		ctl = macb_readl(lp, NCR);

		ctl = macb_readl(lp, NCR);

		macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));

		macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));

		wmb();

		macb_writel(lp, NCR, ctl | MACB_BIT(RE));

		macb_writel(lp, NCR, ctl | MACB_BIT(RE));

	}

	}