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Commit ff6814d5 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Ralf Baechle
Browse files

[MIPS] Alchemy common headers style cleanup 



Fix several errors and warnings given by checkpatch.pl:

- space after opening and before closing parentheses;

- opening brace following 'struct' not on the same line;

- leading spaces instead of tabs;

- use of C99 // comments;

- macros with complex values not enclosed in parentheses;

- missing space between the type and asterisk in a variable declaration;

- space between asterisk and function name;

- including <asm/io.h> instead of <linux/io.h> and <asm/irq.h> instead of
  <linux/irq.h>;

- use of '__inline__' instead of 'inline';

- space between function name and opening parenthesis;

- line over 80 characters.

In addition to these changes, also do the following:

- remove needless parentheses;

- insert spaces between operator and its operands;

- replace spaces after the macro name with tabs in the #define directives and
  after the type in the structure field declarations;

- remove excess tabs after the macro name in the #define directives and in the
  'extern' variable declarations;

- remove excess spaces between # and define for the SSI_*_MASK macros to align
  with other such macros;

- put '||' operator on the same line with its first operand;

- properly indent multi-line function prototypes;

- make the multi-line comment style consistent with the kernel style elsewhere
  by adding empty first line and/or adding space/asterisk on their left side;

- make two-line comments that only have one line of text one-line;

- convert the large multi-line comment in au1xxx_ide.h into several one-liners,
  replace spaces with tabs there;

- fix typos/errors, capitalize acronyms, etc. in the comments;

- insert missing and remove excess new lines;

- update MontaVista copyright;

- remove Pete Popov's and Steve Longerbeam's old email addresses...

Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ad1d77a3

include/asm-mips/mach-au1x00/au1000.h

+820 −824
Original line number Diff line number Diff line
@@ -40,8 +40,8 @@ 
#include <linux/delay.h>

#include <linux/types.h>



#include <asm/io.h>

#include <asm/irq.h>

#include <linux/io.h>

#include <linux/irq.h>



/* cpu pipeline flush */

void static inline au_sync(void)
@@ -63,32 +63,32 @@ void static inline au_sync_delay(int ms) 


void static inline au_writeb(u8 val, unsigned long reg)

{

	*(volatile u8 *)(reg) = val;

	*(volatile u8 *)reg = val;

}



void static inline au_writew(u16 val, unsigned long reg)

{

	*(volatile u16 *)(reg) = val;

	*(volatile u16 *)reg = val;

}



void static inline au_writel(u32 val, unsigned long reg)

{

	*(volatile u32 *)(reg) = val;

	*(volatile u32 *)reg = val;

}



static inline u8 au_readb(unsigned long reg)

{

	return (*(volatile u8 *)reg);

	return *(volatile u8 *)reg;

}



static inline u16 au_readw(unsigned long reg)

{

	return (*(volatile u16 *)reg);

	return *(volatile u16 *)reg;

}



static inline u32 au_readl(unsigned long reg)

{

	return (*(volatile u32 *)reg);

	return *(volatile u32 *)reg;

}
@@ -117,23 +117,24 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; 
#endif /* !defined (_LANGUAGE_ASSEMBLY) */



/*

 * SDRAM Register Offsets

 * SDRAM register offsets

 */

#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)

#define MEM_SDMODE0		(0x0000)

#define MEM_SDMODE1		(0x0004)

#define MEM_SDMODE2		(0x0008)

#define MEM_SDADDR0		(0x000C)

#define MEM_SDADDR1		(0x0010)

#define MEM_SDADDR2		(0x0014)

#define MEM_SDREFCFG	(0x0018)

#define MEM_SDPRECMD	(0x001C)

#define MEM_SDAUTOREF	(0x0020)

#define MEM_SDWRMD0		(0x0024)

#define MEM_SDWRMD1		(0x0028)

#define MEM_SDWRMD2		(0x002C)

#define MEM_SDSLEEP		(0x0030)

#define MEM_SDSMCKE		(0x0034)

#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \

    defined(CONFIG_SOC_AU1100)

#define MEM_SDMODE0		0x0000

#define MEM_SDMODE1		0x0004

#define MEM_SDMODE2		0x0008

#define MEM_SDADDR0		0x000C

#define MEM_SDADDR1		0x0010

#define MEM_SDADDR2		0x0014

#define MEM_SDREFCFG		0x0018

#define MEM_SDPRECMD		0x001C

#define MEM_SDAUTOREF		0x0020

#define MEM_SDWRMD0		0x0024

#define MEM_SDWRMD1		0x0028

#define MEM_SDWRMD2		0x002C

#define MEM_SDSLEEP		0x0030

#define MEM_SDSMCKE		0x0034



/*

 * MEM_SDMODE register content definitions
@@ -199,25 +200,25 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; 
/***********************************************************************/



#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)

#define MEM_SDMODE0		(0x0800)

#define MEM_SDMODE1		(0x0808)

#define MEM_SDMODE2		(0x0810)

#define MEM_SDADDR0		(0x0820)

#define MEM_SDADDR1		(0x0828)

#define MEM_SDADDR2		(0x0830)

#define MEM_SDCONFIGA	(0x0840)

#define MEM_SDCONFIGB	(0x0848)

#define MEM_SDSTAT		(0x0850)

#define MEM_SDERRADDR	(0x0858)

#define MEM_SDSTRIDE0	(0x0860)

#define MEM_SDSTRIDE1	(0x0868)

#define MEM_SDSTRIDE2	(0x0870)

#define MEM_SDWRMD0		(0x0880)

#define MEM_SDWRMD1		(0x0888)

#define MEM_SDWRMD2		(0x0890)

#define MEM_SDPRECMD	(0x08C0)

#define MEM_SDAUTOREF	(0x08C8)

#define MEM_SDSREF		(0x08D0)

#define MEM_SDMODE0		0x0800

#define MEM_SDMODE1		0x0808

#define MEM_SDMODE2		0x0810

#define MEM_SDADDR0		0x0820

#define MEM_SDADDR1		0x0828

#define MEM_SDADDR2		0x0830

#define MEM_SDCONFIGA		0x0840

#define MEM_SDCONFIGB		0x0848

#define MEM_SDSTAT		0x0850

#define MEM_SDERRADDR		0x0858

#define MEM_SDSTRIDE0		0x0860

#define MEM_SDSTRIDE1		0x0868

#define MEM_SDSTRIDE2		0x0870

#define MEM_SDWRMD0		0x0880

#define MEM_SDWRMD1		0x0888

#define MEM_SDWRMD2		0x0890

#define MEM_SDPRECMD		0x08C0

#define MEM_SDAUTOREF		0x08C8

#define MEM_SDSREF		0x08D0

#define MEM_SDSLEEP		MEM_SDSREF



#endif
@@ -402,7 +403,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; 
#define PCMCIA_MEM_PHYS_ADDR	0xF80000000ULL

#endif





/* Static Bus Controller */

#define MEM_STCFG0		0xB4001000

#define MEM_STTIME0		0xB4001004
@@ -424,9 +424,9 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; 
#define MEM_STNDCTL		0xB4001100

#define MEM_STSTAT		0xB4001104



#define MEM_STNAND_CMD                  (0x0)

#define MEM_STNAND_ADDR                 (0x4)

#define MEM_STNAND_DATA                (0x20)

#define MEM_STNAND_CMD		0x0

#define MEM_STNAND_ADDR 	0x4

#define MEM_STNAND_DATA 	0x20

#endif



/* Interrupt Controller 0 */
@@ -506,7 +506,7 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; 
#define IC1_TESTBIT		0xB1800080



/* Interrupt Configuration Modes */

#define INTC_INT_DISABLED                0

#define INTC_INT_DISABLED		0x0

#define INTC_INT_RISE_EDGE		0x1

#define INTC_INT_FALL_EDGE		0x2

#define INTC_INT_RISE_AND_FALL_EDGE	0x3
@@ -584,8 +584,8 @@ enum soc_au1000_ints { 
#define UART2_ADDR		0xB1300000

#define UART3_ADDR		0xB1400000



#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap

#define USB_HOST_CONFIG           0xB017fffc

#define USB_OHCI_BASE		0x10100000	/* phys addr for ioremap */

#define USB_HOST_CONFIG 	0xB017FFFC



#define AU1000_ETH0_BASE	0xB0500000

#define AU1000_ETH1_BASE	0xB0510000
@@ -665,7 +665,7 @@ enum soc_au1500_ints { 
#define UART0_ADDR		0xB1100000

#define UART3_ADDR		0xB1400000



#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap

#define USB_OHCI_BASE		0x10100000	/* phys addr for ioremap */

#define USB_HOST_CONFIG 	0xB017fffc



#define AU1500_ETH0_BASE	0xB1500000
@@ -743,8 +743,8 @@ enum soc_au1100_ints { 
#define UART1_ADDR		0xB1200000

#define UART3_ADDR		0xB1400000



#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap

#define USB_HOST_CONFIG           0xB017fffc

#define USB_OHCI_BASE		0x10100000	/* phys addr for ioremap */

#define USB_HOST_CONFIG 	0xB017FFFC



#define AU1100_ETH0_BASE	0xB0500000

#define AU1100_MAC0_ENABLE	0xB0520000
@@ -830,7 +830,7 @@ enum soc_au1550_ints { 
#define UART1_ADDR		0xB1200000

#define UART3_ADDR		0xB1400000



#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap

#define USB_OHCI_BASE		0x14020000	/* phys addr for ioremap */

#define USB_OHCI_LEN		0x00060000

#define USB_HOST_CONFIG 	0xB4027ffc
@@ -989,7 +989,7 @@ enum soc_au1200_ints { 


/* I2S Controller */

#define I2S_DATA		0xB1000000

#  define I2S_DATA_MASK        (0xffffff)

#  define I2S_DATA_MASK 	0xffffff

#define I2S_CONFIG		0xB1000004

#  define I2S_CONFIG_XU 	(1 << 25)

#  define I2S_CONFIG_XO 	(1 << 24)
@@ -1036,7 +1036,7 @@ enum soc_au1200_ints { 
#define USBD_INTSTAT		0xB020001C

#  define USBDEV_INT_SOF	(1 << 12)

#  define USBDEV_INT_HF_BIT	6

#  define USBDEV_INT_HF_MASK   (0x3f << USBDEV_INT_HF_BIT)

#  define USBDEV_INT_HF_MASK	0x3f << USBDEV_INT_HF_BIT)

#  define USBDEV_INT_CMPLT_BIT	0

#  define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)

#define USBD_CONFIG		0xB0200020
@@ -1195,7 +1195,6 @@ enum soc_au1200_ints { 
#define MAC_RX_BUFF3_STATUS	0x30

#define MAC_RX_BUFF3_ADDR	0x34





/* UARTS 0-3 */

#define UART_BASE		UART0_ADDR

#ifdef	CONFIG_SOC_AU1200
@@ -1294,8 +1293,6 @@ enum soc_au1200_ints { 
#define UART_MSR_DCTS	0x01	/* Delta CTS */

#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */







/* SSIO */

#define SSI0_STATUS		0xB1600000

#  define SSI_STATUS_BF 	(1 << 4)
@@ -1384,13 +1381,12 @@ enum soc_au1200_ints { 


#define SSI_ADATA_D		(1 << 24)

#define SSI_ADATA_ADDR		(0xFF << 16)

#define SSI_ADATA_DATA				(0x0FFF)

#define SSI_ADATA_DATA		0x0FFF

#define SSI_ADATA_ADDR_N(N)	(N << 16)



#define SSI_ENABLE_CD		(1 << 1)

#define SSI_ENABLE_E		(1 << 0)





/* IrDA Controller */

#define IRDA_BASE		0xB0300000

#define IR_RING_PTR_STATUS	(IRDA_BASE + 0x00)
@@ -1449,29 +1445,29 @@ enum soc_au1200_ints { 
#  define SYS_PF_A97		(1 << 1)	/* AC97/SSL1 */

#  define SYS_PF_S0		(1 << 0)	/* SSI_0/GPIO[16:18] */



/* Au1100 Only */

/* Au1100 only */

#  define SYS_PF_PC		(1 << 18)	/* PCMCIA/GPIO[207:204] */

#  define SYS_PF_LCD		(1 << 17)	/* extern lcd/GPIO[203:200] */

#  define SYS_PF_CS			(1<<16)	/* EXTCLK0/32khz to gpio2 */

#  define SYS_PF_EX0			(1<<9)	/* gpio2/clock */

#  define SYS_PF_CS		(1 << 16)	/* EXTCLK0/32KHz to gpio2 */

#  define SYS_PF_EX0		(1 << 9)	/* GPIO2/clock */



/* Au1550 Only.  Redefines lots of pins */

/* Au1550 only.  Redefines lots of pins */

#  define SYS_PF_PSC2_MASK	(7 << 17)

#  define SYS_PF_PSC2_AC97		(0)

#  define SYS_PF_PSC2_SPI		(0)

#  define SYS_PF_PSC2_AC97	0

#  define SYS_PF_PSC2_SPI	0

#  define SYS_PF_PSC2_I2S	(1 << 17)

#  define SYS_PF_PSC2_SMBUS	(3 << 17)

#  define SYS_PF_PSC2_GPIO	(7 << 17)

#  define SYS_PF_PSC3_MASK	(7 << 20)

#  define SYS_PF_PSC3_AC97		(0)

#  define SYS_PF_PSC3_SPI		(0)

#  define SYS_PF_PSC3_AC97	0

#  define SYS_PF_PSC3_SPI	0

#  define SYS_PF_PSC3_I2S	(1 << 20)

#  define SYS_PF_PSC3_SMBUS	(3 << 20)

#  define SYS_PF_PSC3_GPIO	(7 << 20)

#  define SYS_PF_PSC1_S1	(1 << 1)

#  define SYS_PF_MUST_BE_SET	((1 << 5) | (1 << 2))



/* Au1200 Only */

/* Au1200 only */

#ifdef CONFIG_SOC_AU1200

#define SYS_PINFUNC_DMA 	(1 << 31)

#define SYS_PINFUNC_S0A 	(1 << 30)
@@ -1629,7 +1625,6 @@ enum soc_au1200_ints { 
#  define AC97C_RS		(1 << 1)

#  define AC97C_CE		(1 << 0)





/* Secure Digital (SD) Controller */

#define SD0_XMIT_FIFO	0xB0600000

#define SD0_RECV_FIFO	0xB0600004
@@ -1638,10 +1633,11 @@ enum soc_au1200_ints { 


#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)

/* Au1500 PCI Controller */

#define Au1500_CFG_BASE           0xB4005000 // virtual, kseg0 addr

#define Au1500_CFG_BASE 	0xB4005000	/* virtual, KSEG1 addr */

#define Au1500_PCI_CMEM 	(Au1500_CFG_BASE + 0)

#define Au1500_PCI_CFG		(Au1500_CFG_BASE + 4)

#  define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))

#  define PCI_ERROR		((1 << 22) | (1 << 23) | (1 << 24) | \

				 (1 << 25) | (1 << 26) | (1 << 27))

#define Au1500_PCI_B2BMASK_CCH	(Au1500_CFG_BASE + 8)

#define Au1500_PCI_B2B0_VID	(Au1500_CFG_BASE + 0xC)

#define Au1500_PCI_B2B1_ID	(Au1500_CFG_BASE + 0x10)
@@ -1655,14 +1651,15 @@ enum soc_au1200_ints { 
#define Au1500_PCI_HDRTYPE	(Au1500_CFG_BASE + 0x10C)

#define Au1500_PCI_MBAR 	(Au1500_CFG_BASE + 0x110)



#define Au1500_PCI_HDR            0xB4005100 // virtual, kseg0 addr

#define Au1500_PCI_HDR		0xB4005100	/* virtual, KSEG1 addr */



/* All of our structures, like pci resource, have 32 bit members.

/*

 * All of our structures, like PCI resource, have 32-bit members.

 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's

 * hard to store 0x4 0000 0000 in a 32 bit type.  We require a small patch

 * hard to store 0x4 0000 0000 in a 32-bit type.  We require a small patch

 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and

 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM

 * addresses.  For PCI IO, it's simpler because we get to do the ioremap

 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM

 * addresses.  For PCI I/O, it's simpler because we get to do the ioremap

 * ourselves and then adjust the device's resources.

 */

#define Au1500_EXT_CFG		0x600000000ULL
@@ -1687,7 +1684,7 @@ enum soc_au1200_ints { 


#else /* Au1000 and Au1100 and Au1200 */



/* don't allow any legacy ports probing */

/* Don't allow any legacy ports probing */

#define IOPORT_RESOURCE_START	0x10000000

#define IOPORT_RESOURCE_END	0xffffffff

#define IOMEM_RESOURCE_START	0x10000000
@@ -1703,8 +1700,7 @@ enum soc_au1200_ints { 
#endif



#ifndef _LANGUAGE_ASSEMBLY

typedef volatile struct

{

typedef volatile struct {

	/* 0x0000 */ u32 toytrim;

	/* 0x0004 */ u32 toywrite;

	/* 0x0008 */ u32 toymatch0;
@@ -1746,13 +1742,14 @@ typedef volatile struct 
	/* 0x010C */ u32 outputclr;

	/* 0x0110 */ u32 pinstaterd;

#define pininputen pinstaterd



} AU1X00_SYS;



static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;



#endif

/* Processor information base on prid.



/*

 * Processor information based on PRID.

 * Copied from PowerPC.

 */

#ifndef _LANGUAGE_ASSEMBLY
@@ -1772,4 +1769,3 @@ extern struct cpu_spec *cur_cpu_spec[]; 
#endif



#endif

include/asm-mips/mach-au1x00/au1000_dma.h

+96 −83
Original line number Diff line number Diff line 
/*

 * BRIEF MODULE DESCRIPTION

 *	Defines for using and allocating dma channels on the Alchemy

 *      Au1000 mips processor.

 *	Defines for using and allocating DMA channels on the Alchemy

 *      Au1x00 MIPS processors.

 *

 * Copyright 2000 MontaVista Software Inc.

 * Author: MontaVista Software, Inc.

 *         	stevel@mvista.com or source@mvista.com

 * Copyright 2000, 2008 MontaVista Software Inc.

 * Author: MontaVista Software, Inc. <source@mvista.com>

 *

 *  This program is free software; you can redistribute  it and/or modify it

 *  under  the terms of  the GNU General  Public License as published by the
@@ -31,7 +30,7 @@ 
#ifndef __ASM_AU1000_DMA_H

#define __ASM_AU1000_DMA_H



#include <asm/io.h>		/* need byte IO */

#include <linux/io.h>		/* need byte IO */

#include <linux/spinlock.h>	/* And spinlocks */

#include <linux/delay.h>

#include <asm/system.h>
@@ -79,7 +78,7 @@ 
#define DMA_COUNT_BIT	0

#define DMA_COUNT_MASK	(0xffff << DMA_COUNT_BIT)



/* DMA Device ID's follow */

/* DMA Device IDs follow */

enum {

	DMA_ID_UART0_TX = 0,

	DMA_ID_UART0_RX,
@@ -110,7 +109,8 @@ enum { 
};



struct dma_chan {

	int dev_id;		// this channel is allocated if >=0, free otherwise

	int dev_id;		/* this channel is allocated if >= 0, */

				/* free otherwise */

	unsigned int io;

	const char *dev_str;

	int irq;
@@ -132,23 +132,23 @@ extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos, 
extern void dump_au1000_dma_channel(unsigned int dmanr);

extern spinlock_t au1000_dma_spin_lock;





static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)

static inline struct dma_chan *get_dma_chan(unsigned int dmanr)

{

	if (dmanr >= NUM_AU1000_DMA_CHANNELS

	    || au1000_dma_table[dmanr].dev_id < 0)

	if (dmanr >= NUM_AU1000_DMA_CHANNELS ||

	    au1000_dma_table[dmanr].dev_id < 0)

		return NULL;

	return &au1000_dma_table[dmanr];

}



static __inline__ unsigned long claim_dma_lock(void)

static inline unsigned long claim_dma_lock(void)

{

	unsigned long flags;



	spin_lock_irqsave(&au1000_dma_spin_lock, flags);

	return flags;

}



static __inline__ void release_dma_lock(unsigned long flags)

static inline void release_dma_lock(unsigned long flags)

{

	spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);

}
@@ -156,48 +156,53 @@ static __inline__ void release_dma_lock(unsigned long flags) 
/*

 * Set the DMA buffer enable bits in the mode register.

 */

static __inline__ void enable_dma_buffer0(unsigned int dmanr)

static inline void enable_dma_buffer0(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	au_writel(DMA_BE0, chan->io + DMA_MODE_SET);

}

static __inline__ void enable_dma_buffer1(unsigned int dmanr)



static inline void enable_dma_buffer1(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	au_writel(DMA_BE1, chan->io + DMA_MODE_SET);

}

static __inline__ void enable_dma_buffers(unsigned int dmanr)

static inline void enable_dma_buffers(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);

}



static __inline__ void start_dma(unsigned int dmanr)

static inline void start_dma(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;



	au_writel(DMA_GO, chan->io + DMA_MODE_SET);

}



#define DMA_HALT_POLL 0x5000



static __inline__ void halt_dma(unsigned int dmanr)

static inline void halt_dma(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);

	int i;



	if (!chan)

		return;



	au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);

	// poll the halt bit



	/* Poll the halt bit */

	for (i = 0; i < DMA_HALT_POLL; i++)

		if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)

			break;
@@ -205,40 +210,41 @@ static __inline__ void halt_dma(unsigned int dmanr) 
		printk(KERN_INFO "halt_dma: HALT poll expired!\n");

}





static __inline__ void disable_dma(unsigned int dmanr)

static inline void disable_dma(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;



	halt_dma(dmanr);



	// now we can disable the buffers

	/* Now we can disable the buffers */

	au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);

}



static __inline__ int dma_halted(unsigned int dmanr)

static inline int dma_halted(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return 1;

	return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;

}



/* initialize a DMA channel */

static __inline__ void init_dma(unsigned int dmanr)

/* Initialize a DMA channel. */

static inline void init_dma(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);

	u32 mode;



	if (!chan)

		return;



	disable_dma(dmanr);



	// set device FIFO address

	au_writel(CPHYSADDR(chan->fifo_addr),

		  chan->io + DMA_PERIPHERAL_ADDR);

	/* Set device FIFO address */

	au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);



	mode = chan->mode | (chan->dev_id << DMA_DID_BIT);

	if (chan->irq)
@@ -249,11 +255,12 @@ static __inline__ void init_dma(unsigned int dmanr) 
}



/*

 * set mode for a specific DMA channel

 * Set mode for a specific DMA channel

 */

static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)

static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	/*
@@ -266,36 +273,37 @@ static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode) 
	chan->mode |= mode;

}



static __inline__ unsigned int get_dma_mode(unsigned int dmanr)

static inline unsigned int get_dma_mode(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return 0;

	return chan->mode;

}



static __inline__ int get_dma_active_buffer(unsigned int dmanr)

static inline int get_dma_active_buffer(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return -1;

	return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;

}





/*

 * set the device FIFO address for a specific DMA channel - only

 * Set the device FIFO address for a specific DMA channel - only

 * applicable to GPO4 and GPO5. All the other devices have fixed

 * FIFO addresses.

 */

static __inline__ void set_dma_fifo_addr(unsigned int dmanr,

					 unsigned int a)

static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;



	if (chan->mode & DMA_DS)	/* second bank of device ids */

	if (chan->mode & DMA_DS)	/* second bank of device IDs */

		return;



	if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
@@ -307,16 +315,19 @@ static __inline__ void set_dma_fifo_addr(unsigned int dmanr, 
/*

 * Clear the DMA buffer done bits in the mode register.

 */

static __inline__ void clear_dma_done0(unsigned int dmanr)

static inline void clear_dma_done0(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);

}

static __inline__ void clear_dma_done1(unsigned int dmanr)



static inline void clear_dma_done1(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
@@ -325,16 +336,17 @@ static __inline__ void clear_dma_done1(unsigned int dmanr) 
/*

 * This does nothing - not applicable to Au1000 DMA.

 */

static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)

static inline void set_dma_page(unsigned int dmanr, char pagenr)

{

}



/*

 * Set Buffer 0 transfer address for specific DMA channel.

 */

static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)

static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	au_writel(a, chan->io + DMA_BUFFER0_START);
@@ -343,9 +355,10 @@ static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a) 
/*

 * Set Buffer 1 transfer address for specific DMA channel.

 */

static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)

static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	au_writel(a, chan->io + DMA_BUFFER1_START);
@@ -355,10 +368,10 @@ static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a) 
/*

 * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.

 */

static __inline__ void set_dma_count0(unsigned int dmanr,

				      unsigned int count)

static inline void set_dma_count0(unsigned int dmanr, unsigned int count)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	count &= DMA_COUNT_MASK;
@@ -368,10 +381,10 @@ static __inline__ void set_dma_count0(unsigned int dmanr, 
/*

 * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.

 */

static __inline__ void set_dma_count1(unsigned int dmanr,

				      unsigned int count)

static inline void set_dma_count1(unsigned int dmanr, unsigned int count)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	count &= DMA_COUNT_MASK;
@@ -381,10 +394,10 @@ static __inline__ void set_dma_count1(unsigned int dmanr, 
/*

 * Set both buffer transfer sizes (max 64k) for a specific DMA channel.

 */

static __inline__ void set_dma_count(unsigned int dmanr,

				     unsigned int count)

static inline void set_dma_count(unsigned int dmanr, unsigned int count)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return;

	count &= DMA_COUNT_MASK;
@@ -396,12 +409,12 @@ static __inline__ void set_dma_count(unsigned int dmanr, 
 * Returns which buffer has its done bit set in the mode register.

 * Returns -1 if neither or both done bits set.

 */

static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr)

static inline unsigned int get_dma_buffer_done(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return 0;



	return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);

}
@@ -409,22 +422,23 @@ static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr) 
/*

 * Returns the DMA channel's Buffer Done IRQ number.

 */

static __inline__ int get_dma_done_irq(unsigned int dmanr)

static inline int get_dma_done_irq(unsigned int dmanr)

{

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return -1;



	return chan->irq;

}



/*

 * Get DMA residue count. Returns the number of _bytes_ left to transfer.

 */

static __inline__ int get_dma_residue(unsigned int dmanr)

static inline int get_dma_residue(unsigned int dmanr)

{

	int curBufCntReg, count;

	struct dma_chan *chan = get_dma_chan(dmanr);



	if (!chan)

		return 0;
@@ -442,4 +456,3 @@ static __inline__ int get_dma_residue(unsigned int dmanr) 
}



#endif /* __ASM_AU1000_DMA_H */

include/asm-mips/mach-au1x00/au1000_gpio.h

+9 −9
Original line number Diff line number Diff line
@@ -2,12 +2,12 @@ 
 * FILE NAME au1000_gpio.h

 *

 * BRIEF MODULE DESCRIPTION

 *	API to Alchemy Au1000 GPIO device.

 *	API to Alchemy Au1xx0 GPIO device.

 *

 *  Author: MontaVista Software, Inc.  <source@mvista.com>

 *          Steve Longerbeam <stevel@mvista.com>

 *          Steve Longerbeam

 *

 * Copyright 2001 MontaVista Software Inc.

 * Copyright 2001, 2008 MontaVista Software Inc.

 *

 *  This program is free software; you can redistribute  it and/or modify it

 *  under  the terms of  the GNU General  Public License as published by the

include/asm-mips/mach-au1x00/au1550_spi.h

+1 −1
Original line number Diff line number Diff line 
/*

 * au1550_spi.h - au1550 psc spi controller driver - platform data struct

 * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure

 */



#ifndef _AU1550_SPI_H_

include/asm-mips/mach-au1x00/au1xxx.h

+2 −2
Original line number Diff line number Diff line
@@ -23,10 +23,10 @@ 
#ifndef _AU1XXX_H_

#define _AU1XXX_H_





#include <asm/mach-au1x00/au1000.h>



#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)

#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \

    defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)

#include <asm/mach-db1x00/db1x00.h>



#elif defined(CONFIG_MIPS_PB1550)