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Commit ff6132e9 authored by Ravikishore Pampana's avatar Ravikishore Pampana Committed by Karthik Anantha Ram
Browse files

msm: camera: isp: Add support for dual isp 



Add support for dual ISP. Change allows for address sync,
external regupdate and image address configuraion for dual
case. Also adds csid test gen for dual isp.

Change-Id: Id3cb4b45c3562f7257007bc2b91436d07e26a368
Signed-off-by: default avatarRavikishore Pampana <rpampana@codeaurora.org>
Signed-off-by: default avatarKarthik Anantha Ram <kartanan@codeaurora.org>
parent e31ae4b4

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c

+35 −20
Original line number Diff line number Diff line
@@ -496,6 +496,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_rdi( 
		vfe_acquire.vfe_out.out_port_info = out_port;

		vfe_acquire.vfe_out.split_id = CAM_ISP_HW_SPLIT_LEFT;

		vfe_acquire.vfe_out.unique_id = ife_ctx->ctx_index;

		vfe_acquire.vfe_out.is_dual = 0;

		hw_intf = ife_src_res->hw_res[0]->hw_intf;

		rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv,

			&vfe_acquire,
@@ -835,6 +836,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_csid_ipp( 


	if (csid_res->is_dual_vfe) {

		csid_acquire.sync_mode = CAM_ISP_HW_SYNC_SLAVE;

		csid_acquire.master_idx = csid_res->hw_res[0]->hw_intf->hw_idx;



		for (j = i + 1; j < CAM_IFE_CSID_HW_NUM_MAX; j++) {

			if (!ife_hw_mgr->csid_devices[j])
@@ -1039,13 +1041,6 @@ static int cam_ife_mgr_acquire_cid_res( 
	struct cam_hw_intf                  *hw_intf;

	struct cam_csid_hw_reserve_resource_args  csid_acquire;



	/* no dual vfe for TPG */

	if ((in_port->res_type == CAM_ISP_IFE_IN_RES_TPG) &&

		(in_port->usage_type != 0)) {

		CAM_ERR(CAM_ISP, "No Dual VFE on TPG input");

		goto err;

	}



	ife_hw_mgr = ife_ctx->hw_mgr;



	rc = cam_ife_hw_mgr_get_res(&ife_ctx->free_res_list, &cid_res);
@@ -1984,7 +1979,8 @@ static int cam_ife_mgr_prepare_hw_update(void *hw_mgr_priv, 
		/* get command buffers */

		if (ctx->base[i].split_id != CAM_ISP_HW_SPLIT_MAX) {

			rc = cam_isp_add_command_buffers(prepare,

				ctx->base[i].split_id);

			ctx->base[i].split_id, ctx->base[i].idx,

			ctx->res_list_ife_out, CAM_IFE_HW_OUT_RES_MAX);

				if (rc) {

					CAM_ERR(CAM_ISP,

						"Failed in add cmdbuf, i=%d, split_id=%d, rc=%d",
@@ -2531,7 +2527,7 @@ static int cam_ife_hw_mgr_check_irq_for_dual_vfe( 
	case CAM_ISP_HW_EVENT_SOF:

		event_cnt = ife_hw_mgr_ctx->sof_cnt;

		break;

	case CAM_ISP_HW_EVENT_REG_UPDATE:

	case CAM_ISP_HW_EVENT_EPOCH:

		event_cnt = ife_hw_mgr_ctx->epoch_cnt;

		break;

	case CAM_ISP_HW_EVENT_EOF:
@@ -2551,8 +2547,10 @@ static int cam_ife_hw_mgr_check_irq_for_dual_vfe( 
		return rc;

	}



	if ((event_cnt[core_idx0] - event_cnt[core_idx1] > 1) ||

		(event_cnt[core_idx1] - event_cnt[core_idx0] > 1)) {

	if ((event_cnt[core_idx0] &&

		(event_cnt[core_idx0] - event_cnt[core_idx1] > 1)) ||

		(event_cnt[core_idx1] &&

		(event_cnt[core_idx1] - event_cnt[core_idx0] > 1))) {



		CAM_WARN(CAM_ISP,

			"One of the VFE cound not generate hw event %d",
@@ -2639,6 +2637,8 @@ static int cam_ife_hw_mgr_handle_epoch_for_camif_hw_res( 


				if (!epoch_status)

					ife_hwr_mgr_ctx->epoch_cnt[core_idx]++;

				else

					break;

			}



			/* SOF check for Right side VFE */
@@ -2648,6 +2648,8 @@ static int cam_ife_hw_mgr_handle_epoch_for_camif_hw_res( 


				if (!epoch_status)

					ife_hwr_mgr_ctx->epoch_cnt[core_idx]++;

				else

					break;

			}



			core_index0 = hw_res_l->hw_intf->hw_idx;
@@ -2750,6 +2752,8 @@ static int cam_ife_hw_mgr_process_camif_sof( 
				hw_res_l, evt_payload);

			if (!sof_status)

				ife_hwr_mgr_ctx->sof_cnt[core_idx]++;

			else

				break;

		}



		/* SOF check for Right side VFE */
@@ -2765,6 +2769,8 @@ static int cam_ife_hw_mgr_process_camif_sof( 
				evt_payload);

			if (!sof_status)

				ife_hwr_mgr_ctx->sof_cnt[core_idx]++;

			else

				break;

		}



		core_index0 = hw_res_l->hw_intf->hw_idx;
@@ -2943,6 +2949,8 @@ static int cam_ife_hw_mgr_handle_eof_for_camif_hw_res( 


				if (!eof_status)

					ife_hwr_mgr_ctx->eof_cnt[core_idx]++;

				else

					break;

			}



			/* EOF check for Right side VFE */
@@ -2952,6 +2960,8 @@ static int cam_ife_hw_mgr_handle_eof_for_camif_hw_res( 


				if (!eof_status)

					ife_hwr_mgr_ctx->eof_cnt[core_idx]++;

				else

					break;

			}



			core_index0 = hw_res_l->hw_intf->hw_idx;
@@ -2966,7 +2976,7 @@ static int cam_ife_hw_mgr_handle_eof_for_camif_hw_res( 
			if (!rc)

				ife_hwr_irq_eof_cb(

					ife_hwr_mgr_ctx->common.cb_priv,

					CAM_ISP_HW_EVENT_EPOCH,

					CAM_ISP_HW_EVENT_EOF,

					&eof_done_event_data);



			break;
@@ -3026,6 +3036,8 @@ static int cam_ife_hw_mgr_handle_buf_done_for_hw_res( 
			hw_res_l->hw_intf->hw_idx))

			buf_done_status = hw_res_l->bottom_half_handler(

				hw_res_l, evt_payload);

		else

			continue;



		switch (buf_done_status) {

		case CAM_VFE_IRQ_STATUS_ERR_COMP:
@@ -3125,7 +3137,8 @@ int cam_ife_mgr_do_tasklet_buf_done(void *handler_priv, 
	evt_payload = evt_payload_priv;

	ife_hwr_mgr_ctx = (struct cam_ife_hw_mgr_ctx *)evt_payload->ctx;



	CAM_DBG(CAM_ISP, "addr of evt_payload = %llx", (uint64_t)evt_payload);

	CAM_DBG(CAM_ISP, "addr of evt_payload = %llx core index:0x%x",

		(uint64_t)evt_payload, evt_payload->core_index);

	CAM_DBG(CAM_ISP, "bus_irq_status_0: = %x", evt_payload->irq_reg_val[0]);

	CAM_DBG(CAM_ISP, "bus_irq_status_1: = %x", evt_payload->irq_reg_val[1]);

	CAM_DBG(CAM_ISP, "bus_irq_status_2: = %x", evt_payload->irq_reg_val[2]);
@@ -3155,7 +3168,9 @@ int cam_ife_mgr_do_tasklet(void *handler_priv, void *evt_payload_priv) 
	evt_payload = evt_payload_priv;

	ife_hwr_mgr_ctx = (struct cam_ife_hw_mgr_ctx *)handler_priv;



	CAM_DBG(CAM_ISP, "addr of evt_payload = %llx", (uint64_t)evt_payload);

	CAM_DBG(CAM_ISP, "addr of evt_payload = %pK core_index:%d",

		(void *)evt_payload,

		evt_payload->core_index);

	CAM_DBG(CAM_ISP, "irq_status_0: = %x", evt_payload->irq_reg_val[0]);

	CAM_DBG(CAM_ISP, "irq_status_1: = %x", evt_payload->irq_reg_val[1]);

	CAM_DBG(CAM_ISP, "Violation register: = %x",

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c

+65 −1
Original line number Diff line number Diff line
@@ -82,10 +82,66 @@ int cam_isp_add_change_base( 
	return rc;

}



static int cam_isp_update_dual_config(

	struct cam_hw_prepare_update_args  *prepare,

	struct cam_cmd_buf_desc            *cmd_desc,

	uint32_t                            split_id,

	uint32_t                            base_idx,

	struct cam_ife_hw_mgr_res          *res_list_isp_out,

	uint32_t                            size_isp_out)

{

	int rc = -EINVAL;

	struct cam_isp_dual_config                 *dual_config;

	struct cam_ife_hw_mgr_res                  *hw_mgr_res;

	struct cam_isp_resource_node               *res;

	struct cam_isp_hw_dual_isp_update_args      dual_isp_update_args;

	size_t                                      len = 0;

	uint32_t                                   *cpu_addr;

	uint32_t                                    i, j;



	CAM_DBG(CAM_UTIL, "cmd des size %d, length: %d",

		cmd_desc->size, cmd_desc->length);



	rc = cam_packet_util_get_cmd_mem_addr(

		cmd_desc->mem_handle, &cpu_addr, &len);

	if (rc)

		return rc;



	cpu_addr += (cmd_desc->offset / 4);

	dual_config = (struct cam_isp_dual_config *)cpu_addr;



	for (i = 0; i < dual_config->num_ports; i++) {

		hw_mgr_res = &res_list_isp_out[i];

		for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) {

			if (!hw_mgr_res->hw_res[j])

				continue;



			if (hw_mgr_res->hw_res[j]->hw_intf->hw_idx != base_idx)

				continue;



			res = hw_mgr_res->hw_res[j];

			dual_isp_update_args.split_id = j;

			dual_isp_update_args.res      = res;

			dual_isp_update_args.dual_cfg = dual_config;

			rc = res->hw_intf->hw_ops.process_cmd(

				res->hw_intf->hw_priv,

				CAM_VFE_HW_CMD_STRIPE_UPDATE,

				&dual_isp_update_args,

				sizeof(struct cam_isp_hw_dual_isp_update_args));

			if (rc)

				return rc;

		}

	}



	return rc;

}



int cam_isp_add_command_buffers(

	struct cam_hw_prepare_update_args  *prepare,

	uint32_t                            split_id)

	enum cam_isp_hw_split_id            split_id,

	uint32_t                            base_idx,

	struct cam_ife_hw_mgr_res          *res_list_isp_out,

	uint32_t                            size_isp_out)

{

	int rc = 0;

	uint32_t  cmd_meta_data, num_ent, i;
@@ -168,6 +224,14 @@ int cam_isp_add_command_buffers( 


			num_ent++;

			break;

		case CAM_ISP_PACKET_META_DUAL_CONFIG:

			rc = cam_isp_update_dual_config(prepare,

				&cmd_desc[i], split_id, base_idx,

				res_list_isp_out, size_isp_out);



			if (rc)

				return rc;

			break;

		case CAM_ISP_PACKET_META_GENERIC_BLOB:

			break;

		default:

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h

+9 −4
Original line number Diff line number Diff line
@@ -54,14 +54,19 @@ int cam_isp_add_change_base( 
 *                         left or right VFE/IFE instance.

 *

 * @prepare:               Contain the  packet and HW update variables

 * @dual_type:             Left of right command buffers to be extracted

 *

 * @split_id:              Left or right command buffers to be extracted

 * @base_idx:              Base or dev index of the IFE/VFE HW instance

 * @res_list_isp_out:      IFE /VFE out resource list

 * @size_isp_out:          Size of the res_list_isp_out array

 * @return:                0 for success

 *                         -EINVAL for Fail

 */

int cam_isp_add_command_buffers(

	struct cam_hw_prepare_update_args  *prepare,

	enum cam_isp_hw_split_id              split_id);

	enum cam_isp_hw_split_id            split_id,

	uint32_t                            base_idx,

	struct cam_ife_hw_mgr_res          *res_list_isp_out,

	uint32_t                            size_isp_out);



/**

 * @brief                  Add io buffer configurations in the HW entries list

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h

+2 −1
Original line number Diff line number Diff line
@@ -247,6 +247,7 @@ static struct cam_ife_csid_csi2_tpg_reg_offset 
	/* configurations */

	.tpg_dtn_cfg_offset                           = 0xc,

	.tpg_cgen_cfg_offset                          = 0x20,

	.tpg_cpas_ife_reg_offset                      = 0x28,

};



static struct cam_ife_csid_common_reg_offset

drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c

+71 −23
Original line number Diff line number Diff line
@@ -562,7 +562,7 @@ static int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, 
	struct cam_ife_csid_cid_data       *cid_data;



	CAM_DBG(CAM_ISP,

		"CSID:%d res_sel:%d Lane type:%d lane_num:%d dt:%d vc:%d",

		"CSID:%d res_sel:0x%x Lane type:%d lane_num:%d dt:%d vc:%d",

		csid_hw->hw_intf->hw_idx,

		cid_reserv->in_port->res_type,

		cid_reserv->in_port->lane_type,
@@ -683,11 +683,24 @@ static int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, 
			}

			csid_hw->tpg_cfg.in_format =

				cid_reserv->in_port->format;

			csid_hw->tpg_cfg.usage_type =

				cid_reserv->in_port->usage_type;

			if (cid_reserv->in_port->usage_type)

				csid_hw->tpg_cfg.width =

					(cid_reserv->in_port->right_stop + 1);

			else

				csid_hw->tpg_cfg.width =

					cid_reserv->in_port->left_width;



			csid_hw->tpg_cfg.height = cid_reserv->in_port->height;

			csid_hw->tpg_cfg.test_pattern =

				cid_reserv->in_port->test_pattern;



			CAM_DBG(CAM_ISP, "CSID:%d TPG width:%d height:%d",

				csid_hw->hw_intf->hw_idx,

				csid_hw->tpg_cfg.width,

				csid_hw->tpg_cfg.height);



			cid_data->tpg_set = 1;

		} else {

			csid_hw->csi2_rx_cfg.phy_sel =
@@ -815,6 +828,7 @@ static int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw, 
	path_data->sync_mode = reserve->sync_mode;

	path_data->height  = reserve->in_port->height;

	path_data->start_line = reserve->in_port->line_start;

	path_data->end_line = reserve->in_port->line_stop;

	if (reserve->in_port->res_type == CAM_ISP_IFE_IN_RES_TPG) {

		path_data->dt = CAM_IFE_CSID_TPG_DT_VAL;

		path_data->vc = CAM_IFE_CSID_TPG_VC_VAL;
@@ -826,11 +840,25 @@ static int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw, 
	if (reserve->sync_mode == CAM_ISP_HW_SYNC_MASTER) {

		path_data->crop_enable = 1;

		path_data->start_pixel = reserve->in_port->left_start;

		path_data->end_pixel = reserve->in_port->left_stop;

		path_data->width  = reserve->in_port->left_width;

		CAM_DBG(CAM_ISP, "CSID:%dmaster:startpixel 0x%x endpixel:0x%x",

			csid_hw->hw_intf->hw_idx, path_data->start_pixel,

			path_data->end_pixel);

		CAM_DBG(CAM_ISP, "CSID:%dmaster:line start:0x%x line end:0x%x",

			csid_hw->hw_intf->hw_idx, path_data->start_line,

			path_data->end_line);

	} else if (reserve->sync_mode == CAM_ISP_HW_SYNC_SLAVE) {

		path_data->crop_enable = 1;

		path_data->start_pixel = reserve->in_port->right_start;

		path_data->end_pixel = reserve->in_port->right_stop;

		path_data->width  = reserve->in_port->right_width;

		CAM_DBG(CAM_ISP, "CSID:%d slave:start:0x%x end:0x%x width 0x%x",

			csid_hw->hw_intf->hw_idx, path_data->start_pixel,

			path_data->end_pixel, path_data->width);

		CAM_DBG(CAM_ISP, "CSID:%dmaster:line start:0x%x line end:0x%x",

			csid_hw->hw_intf->hw_idx, path_data->start_line,

			path_data->end_line);

	} else {

		path_data->crop_enable = 0;

		path_data->width  = reserve->in_port->left_width;
@@ -994,6 +1022,7 @@ static int cam_ife_csid_disable_hw(struct cam_ife_csid_hw *csid_hw) 
static int cam_ife_csid_tpg_start(struct cam_ife_csid_hw   *csid_hw,

	struct cam_isp_resource_node       *res)

{

	int rc = 0;

	uint32_t  val = 0;

	struct cam_hw_soc_info    *soc_info;
@@ -1039,6 +1068,15 @@ static int cam_ife_csid_tpg_start(struct cam_ife_csid_hw *csid_hw, 
			}

		}



		/* Enable the IFE force clock on for dual isp case */

		if (csid_hw->tpg_cfg.usage_type) {

			rc = cam_ife_csid_enable_ife_force_clock_on(soc_info,

				csid_hw->csid_info->csid_reg->tpg_reg->

				tpg_cpas_ife_reg_offset);

			if (rc)

				return rc;

		}



		CAM_DBG(CAM_ISP, "============ TPG control ============");

		val = (4 << 20);

		val |= (0x80 << 8);
@@ -1058,6 +1096,7 @@ static int cam_ife_csid_tpg_start(struct cam_ife_csid_hw *csid_hw, 
static int cam_ife_csid_tpg_stop(struct cam_ife_csid_hw   *csid_hw,

	struct cam_isp_resource_node       *res)

{

	int rc = 0;

	struct cam_hw_soc_info    *soc_info;



	if (csid_hw->tpg_start_cnt)
@@ -1073,6 +1112,12 @@ static int cam_ife_csid_tpg_stop(struct cam_ife_csid_hw *csid_hw, 
		CAM_DBG(CAM_ISP, "CSID:%d stop CSID TPG",

			csid_hw->hw_intf->hw_idx);



		/* Disable the IFE force clock on for dual isp case */

		if (csid_hw->tpg_cfg.usage_type)

			rc = cam_ife_csid_disable_ife_force_clock_on(soc_info,

				csid_hw->csid_info->csid_reg->tpg_reg->

				tpg_cpas_ife_reg_offset);



		/*stop the TPG */

		cam_io_w_mb(0,  soc_info->reg_map[0].mem_base +

		csid_hw->csid_info->csid_reg->tpg_reg->csid_tpg_ctrl_addr);
@@ -1100,8 +1145,8 @@ static int cam_ife_csid_config_tpg(struct cam_ife_csid_hw *csid_hw, 
	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

			csid_reg->tpg_reg->csid_tpg_vc_cfg0_addr);



	/* vertical blanking count = 0x740, horzontal blanking count = 0x740*/

	val = (0x740 << 12) | 0x740;

	/* vertical blanking count = 0x3FF, horzontal blanking count = 0x740*/

	val = (0x3FF << 12) | 0x740;

	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

			csid_reg->tpg_reg->csid_tpg_vc_cfg1_addr);
@@ -1299,9 +1344,9 @@ static int cam_ife_csid_init_config_ipp_path( 
		(path_data->dt << csid_reg->cmn_reg->dt_shift_val) |

		(path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) |

		(decode_format << csid_reg->cmn_reg->fmt_shift_val) |

		(path_data->crop_enable & 1 <<

		(path_data->crop_enable <<

		csid_reg->cmn_reg->crop_h_en_shift_val) |

		(path_data->crop_enable & 1 <<

		(path_data->crop_enable <<

		csid_reg->cmn_reg->crop_v_en_shift_val) |

		(1 << 1) | 1;

	val |= (1 << csid_reg->ipp_reg->pix_store_en_shift_val);
@@ -1313,21 +1358,21 @@ static int cam_ife_csid_init_config_ipp_path( 
		csid_reg->ipp_reg->csid_ipp_cfg1_addr);



	if (path_data->crop_enable) {

		val = ((path_data->width +

			path_data->start_pixel) & 0xFFFF <<

		val = (((path_data->end_pixel & 0xFFFF) <<

			csid_reg->cmn_reg->crop_shift) |

			(path_data->start_pixel & 0xFFFF);



			(path_data->start_pixel & 0xFFFF));

		cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

			csid_reg->ipp_reg->csid_ipp_hcrop_addr);

		CAM_DBG(CAM_ISP, "CSID:%d Horizontal crop config val: 0x%x",

			csid_hw->hw_intf->hw_idx, val);



		val = ((path_data->height +

			path_data->start_line) & 0xFFFF <<

		val = (((path_data->end_line & 0xFFFF) <<

			csid_reg->cmn_reg->crop_shift) |

			(path_data->start_line & 0xFFFF);



			(path_data->start_line & 0xFFFF));

		cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

			csid_reg->ipp_reg->csid_ipp_vcrop_addr);

		CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x",

			csid_hw->hw_intf->hw_idx, val);

	}



	/* set frame drop pattern to 0 and period to 1 */
@@ -1623,9 +1668,9 @@ static int cam_ife_csid_init_config_rdi_path( 
		(path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) |

		(path_format << csid_reg->cmn_reg->fmt_shift_val) |

		(plain_fmt << csid_reg->cmn_reg->plain_fmt_shit_val) |

		(path_data->crop_enable & 1 <<

		(path_data->crop_enable  <<

			csid_reg->cmn_reg->crop_h_en_shift_val) |

		(path_data->crop_enable & 1 <<

		(path_data->crop_enable  <<

		csid_reg->cmn_reg->crop_v_en_shift_val) |

		(1 << 2) | 3;
@@ -1637,21 +1682,23 @@ static int cam_ife_csid_init_config_rdi_path( 
			csid_reg->rdi_reg[id]->csid_rdi_cfg1_addr);



	if (path_data->crop_enable) {

		val = ((path_data->width +

			path_data->start_pixel) & 0xFFFF <<

		val = (((path_data->end_pixel & 0xFFFF) <<

			csid_reg->cmn_reg->crop_shift) |

			(path_data->start_pixel & 0xFFFF);

			(path_data->start_pixel & 0xFFFF));



		cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

			csid_reg->rdi_reg[id]->csid_rdi_rpp_hcrop_addr);

		CAM_DBG(CAM_ISP, "CSID:%d Horizontal crop config val: 0x%x",

			csid_hw->hw_intf->hw_idx, val);



		val = ((path_data->height +

			path_data->start_line) & 0xFFFF <<

		val = (((path_data->end_line & 0xFFFF) <<

			csid_reg->cmn_reg->crop_shift) |

			(path_data->start_line & 0xFFFF);

			(path_data->start_line & 0xFFFF));



		cam_io_w_mb(val, soc_info->reg_map[0].mem_base +

			csid_reg->rdi_reg[id]->csid_rdi_rpp_vcrop_addr);

		CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x",

			csid_hw->hw_intf->hw_idx, val);

	}

	/* set frame drop pattern to 0 and period to 1 */

	cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
@@ -2683,6 +2730,7 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) 
			CAM_DBG(CAM_ISP, "CSID IPP reset complete");

			complete(&csid_hw->csid_ipp_complete);

		}



		if ((irq_status_ipp & CSID_PATH_INFO_INPUT_SOF) &&

			(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ))

			CAM_ERR(CAM_ISP, "CSID:%d IPP SOF received",