staging: brcm80211: remove usage of struct osl_info for register access (ff31c54c) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/staging/brcm80211/brcmfmac/dhd_sdio.c

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -391,7 +391,7 @@ static bool dhd_readahead;
	do { \		do { \
	retryvar = 0; \		retryvar = 0; \
	do { \		do { \
	regvar = R_REG(bus->dhd->osh, regaddr); \		regvar = R_REG(regaddr); \
	} while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \		} while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
	if (retryvar) { \		if (retryvar) { \
	bus->regfails += (retryvar-1); \		bus->regfails += (retryvar-1); \
	@@ -407,7 +407,7 @@ do { \
	do { \		do { \
	retryvar = 0; \		retryvar = 0; \
	do { \		do { \
	W_REG(bus->dhd->osh, regaddr, regval); \		W_REG(regaddr, regval); \
	} while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \		} while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
	if (retryvar) { \		if (retryvar) { \
	bus->regfails += (retryvar-1); \		bus->regfails += (retryvar-1); \
	@@ -5370,7 +5370,7 @@ dhdsdio_probe_attach(struct dhd_bus bus, struct osl_info osh, void *sdh,
	bus->sdpcmrev = si_corerev(bus->sih);		bus->sdpcmrev = si_corerev(bus->sih);

	/* Set core control so an SDIO reset does a backplane reset */		/* Set core control so an SDIO reset does a backplane reset */
	OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);		OR_REG(&bus->regs->corecontrol, CC_BPRESEN);

	pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);		pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);

drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c

+85 −85

Original line number	Original line	Diff line number	Diff line
	@@ -212,7 +212,7 @@ void wlc_radioreg_exit(wlc_phy_t *pih)
	phy_info_t pi = (phy_info_t ) pih;		phy_info_t pi = (phy_info_t ) pih;
	volatile u16 dummy;		volatile u16 dummy;

	dummy = R_REG(pi->sh->osh, &pi->regs->phyversion);		dummy = R_REG(&pi->regs->phyversion);
	pi->phy_wreg = 0;		pi->phy_wreg = 0;
	wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0);		wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0);
	}		}
	@@ -248,23 +248,23 @@ u16 read_radio_reg(phy_info_t *pi, u16 addr)
	if ((D11REV_GE(pi->sh->corerev, 24)) \|\|		if ((D11REV_GE(pi->sh->corerev, 24)) \|\|
	(D11REV_IS(pi->sh->corerev, 22)		(D11REV_IS(pi->sh->corerev, 22)
	&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {		&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
	W_REG(pi->sh->osh, &pi->regs->radioregaddr, addr);		W_REG(&pi->regs->radioregaddr, addr);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);		(void)R_REG(&pi->regs->radioregaddr);
	#endif		#endif
	data = R_REG(pi->sh->osh, &pi->regs->radioregdata);		data = R_REG(&pi->regs->radioregdata);
	} else {		} else {
	W_REG(pi->sh->osh, &pi->regs->phy4waddr, addr);		W_REG(&pi->regs->phy4waddr, addr);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(pi->sh->osh, &pi->regs->phy4waddr);		(void)R_REG(&pi->regs->phy4waddr);
	#endif		#endif

	#ifdef __ARM_ARCH_4T__		#ifdef __ARM_ARCH_4T__
	__asm__(" .align 4 ");		__asm__(" .align 4 ");
	__asm__(" nop ");		__asm__(" nop ");
	data = R_REG(pi->sh->osh, &pi->regs->phy4wdatalo);		data = R_REG(&pi->regs->phy4wdatalo);
	#else		#else
	data = R_REG(pi->sh->osh, &pi->regs->phy4wdatalo);		data = R_REG(&pi->regs->phy4wdatalo);
	#endif		#endif

	}		}
	@@ -286,22 +286,22 @@ void write_radio_reg(phy_info_t *pi, u16 addr, u16 val)
	(D11REV_IS(pi->sh->corerev, 22)		(D11REV_IS(pi->sh->corerev, 22)
	&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {		&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {

	W_REG(osh, &pi->regs->radioregaddr, addr);		W_REG(&pi->regs->radioregaddr, addr);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(osh, &pi->regs->radioregaddr);		(void)R_REG(&pi->regs->radioregaddr);
	#endif		#endif
	W_REG(osh, &pi->regs->radioregdata, val);		W_REG(&pi->regs->radioregdata, val);
	} else {		} else {
	W_REG(osh, &pi->regs->phy4waddr, addr);		W_REG(&pi->regs->phy4waddr, addr);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(osh, &pi->regs->phy4waddr);		(void)R_REG(&pi->regs->phy4waddr);
	#endif		#endif
	W_REG(osh, &pi->regs->phy4wdatalo, val);		W_REG(&pi->regs->phy4wdatalo, val);
	}		}

	if (pi->sh->bustype == PCI_BUS) {		if (pi->sh->bustype == PCI_BUS) {
	if (++pi->phy_wreg >= pi->phy_wreg_limit) {		if (++pi->phy_wreg >= pi->phy_wreg_limit) {
	(void)R_REG(osh, &pi->regs->maccontrol);		(void)R_REG(&pi->regs->maccontrol);
	pi->phy_wreg = 0;		pi->phy_wreg = 0;
	}		}
	}		}
	@@ -317,31 +317,31 @@ static u32 read_radio_id(phy_info_t *pi)
	if (D11REV_GE(pi->sh->corerev, 24)) {		if (D11REV_GE(pi->sh->corerev, 24)) {
	u32 b0, b1, b2;		u32 b0, b1, b2;

	W_REG(pi->sh->osh, &pi->regs->radioregaddr, 0);		W_REG(&pi->regs->radioregaddr, 0);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);		(void)R_REG(&pi->regs->radioregaddr);
	#endif		#endif
	b0 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);		b0 = (u32) R_REG(&pi->regs->radioregdata);
	W_REG(pi->sh->osh, &pi->regs->radioregaddr, 1);		W_REG(&pi->regs->radioregaddr, 1);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);		(void)R_REG(&pi->regs->radioregaddr);
	#endif		#endif
	b1 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);		b1 = (u32) R_REG(&pi->regs->radioregdata);
	W_REG(pi->sh->osh, &pi->regs->radioregaddr, 2);		W_REG(&pi->regs->radioregaddr, 2);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);		(void)R_REG(&pi->regs->radioregaddr);
	#endif		#endif
	b2 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);		b2 = (u32) R_REG(&pi->regs->radioregdata);

	id = ((b0 & 0xf) << 28) \| (((b2 << 8) \| b1) << 12) \| ((b0 >> 4)		id = ((b0 & 0xf) << 28) \| (((b2 << 8) \| b1) << 12) \| ((b0 >> 4)
	& 0xf);		& 0xf);
	} else {		} else {
	W_REG(pi->sh->osh, &pi->regs->phy4waddr, RADIO_IDCODE);		W_REG(&pi->regs->phy4waddr, RADIO_IDCODE);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(pi->sh->osh, &pi->regs->phy4waddr);		(void)R_REG(&pi->regs->phy4waddr);
	#endif		#endif
	id = (u32) R_REG(pi->sh->osh, &pi->regs->phy4wdatalo);		id = (u32) R_REG(&pi->regs->phy4wdatalo);
	id \|= (u32) R_REG(pi->sh->osh, &pi->regs->phy4wdatahi) << 16;		id \|= (u32) R_REG(&pi->regs->phy4wdatahi) << 16;
	}		}
	pi->phy_wreg = 0;		pi->phy_wreg = 0;
	return id;		return id;
	@@ -393,13 +393,13 @@ void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)

	void write_phy_channel_reg(phy_info_t *pi, uint val)		void write_phy_channel_reg(phy_info_t *pi, uint val)
	{		{
	W_REG(pi->sh->osh, &pi->regs->phychannel, val);		W_REG(&pi->regs->phychannel, val);
	}		}

	#if defined(BCMDBG)		#if defined(BCMDBG)
	static bool wlc_phy_war41476(phy_info_t *pi)		static bool wlc_phy_war41476(phy_info_t *pi)
	{		{
	u32 mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);		u32 mc = R_REG(&pi->regs->maccontrol);

	return ((mc & MCTL_EN_MAC) == 0)		return ((mc & MCTL_EN_MAC) == 0)
	\|\| ((mc & MCTL_PHYLOCK) == MCTL_PHYLOCK);		\|\| ((mc & MCTL_PHYLOCK) == MCTL_PHYLOCK);
	@@ -414,9 +414,9 @@ u16 read_phy_reg(phy_info_t *pi, u16 addr)
	osh = pi->sh->osh;		osh = pi->sh->osh;
	regs = pi->regs;		regs = pi->regs;

	W_REG(osh, &regs->phyregaddr, addr);		W_REG(&regs->phyregaddr, addr);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(osh, &regs->phyregaddr);		(void)R_REG(&regs->phyregaddr);
	#endif		#endif

	ASSERT(!		ASSERT(!
	@@ -424,7 +424,7 @@ u16 read_phy_reg(phy_info_t *pi, u16 addr)
	\|\| D11REV_IS(pi->sh->corerev, 12)) \|\| wlc_phy_war41476(pi));		\|\| D11REV_IS(pi->sh->corerev, 12)) \|\| wlc_phy_war41476(pi));

	pi->phy_wreg = 0;		pi->phy_wreg = 0;
	return R_REG(osh, &regs->phyregdata);		return R_REG(&regs->phyregdata);
	}		}

	void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)		void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
	@@ -436,18 +436,18 @@ void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
	regs = pi->regs;		regs = pi->regs;

	#ifdef __mips__		#ifdef __mips__
	W_REG(osh, &regs->phyregaddr, addr);		W_REG(&regs->phyregaddr, addr);
	(void)R_REG(osh, &regs->phyregaddr);		(void)R_REG(&regs->phyregaddr);
	W_REG(osh, &regs->phyregdata, val);		W_REG(&regs->phyregdata, val);
	if (addr == 0x72)		if (addr == 0x72)
	(void)R_REG(osh, &regs->phyregdata);		(void)R_REG(&regs->phyregdata);
	#else		#else
	W_REG(osh, (u32 *)(&regs->phyregaddr),		W_REG((u32 *)(&regs->phyregaddr),
	addr \| (val << 16));		addr \| (val << 16));
	if (pi->sh->bustype == PCI_BUS) {		if (pi->sh->bustype == PCI_BUS) {
	if (++pi->phy_wreg >= pi->phy_wreg_limit) {		if (++pi->phy_wreg >= pi->phy_wreg_limit) {
	pi->phy_wreg = 0;		pi->phy_wreg = 0;
	(void)R_REG(osh, &regs->phyversion);		(void)R_REG(&regs->phyversion);
	}		}
	}		}
	#endif		#endif
	@@ -461,16 +461,16 @@ void and_phy_reg(phy_info_t *pi, u16 addr, u16 val)
	osh = pi->sh->osh;		osh = pi->sh->osh;
	regs = pi->regs;		regs = pi->regs;

	W_REG(osh, &regs->phyregaddr, addr);		W_REG(&regs->phyregaddr, addr);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(osh, &regs->phyregaddr);		(void)R_REG(&regs->phyregaddr);
	#endif		#endif

	ASSERT(!		ASSERT(!
	(D11REV_IS(pi->sh->corerev, 11)		(D11REV_IS(pi->sh->corerev, 11)
	\|\| D11REV_IS(pi->sh->corerev, 12)) \|\| wlc_phy_war41476(pi));		\|\| D11REV_IS(pi->sh->corerev, 12)) \|\| wlc_phy_war41476(pi));

	W_REG(osh, &regs->phyregdata, (R_REG(osh, &regs->phyregdata) & val));		W_REG(&regs->phyregdata, (R_REG(&regs->phyregdata) & val));
	pi->phy_wreg = 0;		pi->phy_wreg = 0;
	}		}

	@@ -482,16 +482,16 @@ void or_phy_reg(phy_info_t *pi, u16 addr, u16 val)
	osh = pi->sh->osh;		osh = pi->sh->osh;
	regs = pi->regs;		regs = pi->regs;

	W_REG(osh, &regs->phyregaddr, addr);		W_REG(&regs->phyregaddr, addr);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(osh, &regs->phyregaddr);		(void)R_REG(&regs->phyregaddr);
	#endif		#endif

	ASSERT(!		ASSERT(!
	(D11REV_IS(pi->sh->corerev, 11)		(D11REV_IS(pi->sh->corerev, 11)
	\|\| D11REV_IS(pi->sh->corerev, 12)) \|\| wlc_phy_war41476(pi));		\|\| D11REV_IS(pi->sh->corerev, 12)) \|\| wlc_phy_war41476(pi));

	W_REG(osh, &regs->phyregdata, (R_REG(osh, &regs->phyregdata) \| val));		W_REG(&regs->phyregdata, (R_REG(&regs->phyregdata) \| val));
	pi->phy_wreg = 0;		pi->phy_wreg = 0;
	}		}

	@@ -503,17 +503,17 @@ void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)
	osh = pi->sh->osh;		osh = pi->sh->osh;
	regs = pi->regs;		regs = pi->regs;

	W_REG(osh, &regs->phyregaddr, addr);		W_REG(&regs->phyregaddr, addr);
	#ifdef __mips__		#ifdef __mips__
	(void)R_REG(osh, &regs->phyregaddr);		(void)R_REG(&regs->phyregaddr);
	#endif		#endif

	ASSERT(!		ASSERT(!
	(D11REV_IS(pi->sh->corerev, 11)		(D11REV_IS(pi->sh->corerev, 11)
	\|\| D11REV_IS(pi->sh->corerev, 12)) \|\| wlc_phy_war41476(pi));		\|\| D11REV_IS(pi->sh->corerev, 12)) \|\| wlc_phy_war41476(pi));

	W_REG(osh, &regs->phyregdata,		W_REG(&regs->phyregdata,
	((R_REG(osh, &regs->phyregdata) & ~mask) \| (val & mask)));		((R_REG(&regs->phyregdata) & ~mask) \| (val & mask)));
	pi->phy_wreg = 0;		pi->phy_wreg = 0;
	}		}

	@@ -658,7 +658,7 @@ wlc_phy_t wlc_phy_attach(shared_phy_t sh, void regs, int bandtype, char vars
	}		}

	wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);		wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
	phyversion = R_REG(osh, &pi->regs->phyversion);		phyversion = R_REG(&pi->regs->phyversion);

	pi->pubpi.phy_type = PHY_TYPE(phyversion);		pi->pubpi.phy_type = PHY_TYPE(phyversion);
	pi->pubpi.phy_rev = phyversion & PV_PV_MASK;		pi->pubpi.phy_rev = phyversion & PV_PV_MASK;
	@@ -985,7 +985,7 @@ void WLBANDINITFN(wlc_phy_init) (wlc_phy_t *pih, chanspec_t chanspec)

	pi->radio_chanspec = chanspec;		pi->radio_chanspec = chanspec;

	mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);		mc = R_REG(&pi->regs->maccontrol);
	if ((mc & MCTL_EN_MAC) != 0) {		if ((mc & MCTL_EN_MAC) != 0) {
	ASSERT((const char *)		ASSERT((const char *)
	"wlc_phy_init: Called with the MAC running!" == NULL);		"wlc_phy_init: Called with the MAC running!" == NULL);
	@@ -1037,7 +1037,7 @@ void wlc_phy_cal_init(wlc_phy_t *pih)
	phy_info_t pi = (phy_info_t ) pih;		phy_info_t pi = (phy_info_t ) pih;
	initfn_t cal_init = NULL;		initfn_t cal_init = NULL;

	ASSERT((R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) == 0);		ASSERT((R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) == 0);

	if (!pi->initialized) {		if (!pi->initialized) {
	cal_init = pi->pi_fptr.calinit;		cal_init = pi->pi_fptr.calinit;
	@@ -1267,34 +1267,34 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
	};		};
	u32 *dummypkt;		u32 *dummypkt;

	ASSERT((R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) == 0);		ASSERT((R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) == 0);

	dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);		dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
	wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,		wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
	dummypkt);		dummypkt);

	W_REG(pi->sh->osh, &regs->xmtsel, 0);		W_REG(&regs->xmtsel, 0);

	if (D11REV_GE(pi->sh->corerev, 11))		if (D11REV_GE(pi->sh->corerev, 11))
	W_REG(pi->sh->osh, &regs->wepctl, 0x100);		W_REG(&regs->wepctl, 0x100);
	else		else
	W_REG(pi->sh->osh, &regs->wepctl, 0);		W_REG(&regs->wepctl, 0);

	W_REG(pi->sh->osh, &regs->txe_phyctl, (ofdm ? 1 : 0) \| PHY_TXC_ANT_0);		W_REG(&regs->txe_phyctl, (ofdm ? 1 : 0) \| PHY_TXC_ANT_0);
	if (ISNPHY(pi) \|\| ISLCNPHY(pi)) {		if (ISNPHY(pi) \|\| ISLCNPHY(pi)) {
	ASSERT(ofdm);		ASSERT(ofdm);
	W_REG(pi->sh->osh, &regs->txe_phyctl1, 0x1A02);		W_REG(&regs->txe_phyctl1, 0x1A02);
	}		}

	W_REG(pi->sh->osh, &regs->txe_wm_0, 0);		W_REG(&regs->txe_wm_0, 0);
	W_REG(pi->sh->osh, &regs->txe_wm_1, 0);		W_REG(&regs->txe_wm_1, 0);

	W_REG(pi->sh->osh, &regs->xmttplatetxptr, 0);		W_REG(&regs->xmttplatetxptr, 0);
	W_REG(pi->sh->osh, &regs->xmttxcnt, DUMMY_PKT_LEN);		W_REG(&regs->xmttxcnt, DUMMY_PKT_LEN);

	W_REG(pi->sh->osh, &regs->xmtsel, ((8 << 8) \| (1 << 5) \| (1 << 2) \| 2));		W_REG(&regs->xmtsel, ((8 << 8) \| (1 << 5) \| (1 << 2) \| 2));

	W_REG(pi->sh->osh, &regs->txe_ctl, 0);		W_REG(&regs->txe_ctl, 0);

	if (!pa_on) {		if (!pa_on) {
	if (ISNPHY(pi))		if (ISNPHY(pi))
	@@ -1302,11 +1302,11 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
	}		}

	if (ISNPHY(pi) \|\| ISLCNPHY(pi))		if (ISNPHY(pi) \|\| ISLCNPHY(pi))
	W_REG(pi->sh->osh, &regs->txe_aux, 0xD0);		W_REG(&regs->txe_aux, 0xD0);
	else		else
	W_REG(pi->sh->osh, &regs->txe_aux, ((1 << 5) \| (1 << 4)));		W_REG(&regs->txe_aux, ((1 << 5) \| (1 << 4)));

	(void)R_REG(pi->sh->osh, &regs->txe_aux);		(void)R_REG(&regs->txe_aux);

	i = 0;		i = 0;
	count = ofdm ? 30 : 250;		count = ofdm ? 30 : 250;
	@@ -1316,22 +1316,22 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
	}		}

	while ((i++ < count)		while ((i++ < count)
	&& (R_REG(pi->sh->osh, &regs->txe_status) & (1 << 7))) {		&& (R_REG(&regs->txe_status) & (1 << 7))) {
	udelay(10);		udelay(10);
	}		}

	i = 0;		i = 0;

	while ((i++ < 10)		while ((i++ < 10)
	&& ((R_REG(pi->sh->osh, &regs->txe_status) & (1 << 10)) == 0)) {		&& ((R_REG(&regs->txe_status) & (1 << 10)) == 0)) {
	udelay(10);		udelay(10);
	}		}

	i = 0;		i = 0;

	while ((i++ < 10) && ((R_REG(pi->sh->osh, &regs->ifsstat) & (1 << 8)))) {		while ((i++ < 10) && ((R_REG(&regs->ifsstat) & (1 << 8))))
	udelay(10);		udelay(10);
	}
	if (!pa_on) {		if (!pa_on) {
	if (ISNPHY(pi))		if (ISNPHY(pi))
	wlc_phy_pa_override_nphy(pi, ON);		wlc_phy_pa_override_nphy(pi, ON);
	@@ -1396,7 +1396,7 @@ void wlc_phy_switch_radio(wlc_phy_t *pih, bool on)
	{		{
	uint mc;		uint mc;

	mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);		mc = R_REG(&pi->regs->maccontrol);
	}		}

	if (ISNPHY(pi)) {		if (ISNPHY(pi)) {
	@@ -1648,7 +1648,7 @@ void wlc_phy_txpower_target_set(wlc_phy_t ppi, struct txpwr_limits txpwr)
	memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SDM],		memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SDM],
	&txpwr->mcs_40_mimo[0], WLC_NUM_RATES_MCS_2_STREAM);		&txpwr->mcs_40_mimo[0], WLC_NUM_RATES_MCS_2_STREAM);

	if (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC)		if (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC)
	mac_enabled = true;		mac_enabled = true;

	if (mac_enabled)		if (mac_enabled)
	@@ -1680,7 +1680,7 @@ int wlc_phy_txpower_set(wlc_phy_t *ppi, uint qdbm, bool override)

	suspend =		suspend =
	(0 ==		(0 ==
	(R_REG(pi->sh->osh, &pi->regs->maccontrol) &		(R_REG(&pi->regs->maccontrol) &
	MCTL_EN_MAC));		MCTL_EN_MAC));

	if (!suspend)		if (!suspend)
	@@ -2096,18 +2096,18 @@ void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end)

	if (NREV_IS(pi->pubpi.phy_rev, 3)		if (NREV_IS(pi->pubpi.phy_rev, 3)
	\|\| NREV_IS(pi->pubpi.phy_rev, 4)) {		\|\| NREV_IS(pi->pubpi.phy_rev, 4)) {
	W_REG(pi->sh->osh, &pi->regs->phyregaddr, 0xa0);		W_REG(&pi->regs->phyregaddr, 0xa0);
	(void)R_REG(pi->sh->osh, &pi->regs->phyregaddr);		(void)R_REG(&pi->regs->phyregaddr);
	rxc = R_REG(pi->sh->osh, &pi->regs->phyregdata);		rxc = R_REG(&pi->regs->phyregdata);
	W_REG(pi->sh->osh, &pi->regs->phyregdata,		W_REG(&pi->regs->phyregdata,
	(0x1 << 15) \| rxc);		(0x1 << 15) \| rxc);
	}		}
	} else {		} else {
	if (NREV_IS(pi->pubpi.phy_rev, 3)		if (NREV_IS(pi->pubpi.phy_rev, 3)
	\|\| NREV_IS(pi->pubpi.phy_rev, 4)) {		\|\| NREV_IS(pi->pubpi.phy_rev, 4)) {
	W_REG(pi->sh->osh, &pi->regs->phyregaddr, 0xa0);		W_REG(&pi->regs->phyregaddr, 0xa0);
	(void)R_REG(pi->sh->osh, &pi->regs->phyregaddr);		(void)R_REG(&pi->regs->phyregaddr);
	W_REG(pi->sh->osh, &pi->regs->phyregdata, rxc);		W_REG(&pi->regs->phyregdata, rxc);
	}		}

	wlc_phy_por_inform(ppi);		wlc_phy_por_inform(ppi);
	@@ -2234,7 +2234,7 @@ void wlc_phy_txpower_hw_ctrl_set(wlc_phy_t *ppi, bool hwpwrctrl)
	if (ISNPHY(pi)) {		if (ISNPHY(pi)) {
	suspend =		suspend =
	(0 ==		(0 ==
	(R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!suspend)		if (!suspend)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);

	@@ -2476,7 +2476,7 @@ void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val)
	return;		return;

	suspend =		suspend =
	(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!suspend)		if (!suspend)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);

	@@ -2590,7 +2590,7 @@ wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch)
	wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);		wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
	wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);		wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);

	OR_REG(pi->sh->osh, &pi->regs->maccommand,		OR_REG(&pi->regs->maccommand,
	MCMD_BG_NOISE);		MCMD_BG_NOISE);
	} else {		} else {
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);
	@@ -2609,7 +2609,7 @@ wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch)
	wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);		wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
	wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);		wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);

	OR_REG(pi->sh->osh, &pi->regs->maccommand,		OR_REG(&pi->regs->maccommand,
	MCMD_BG_NOISE);		MCMD_BG_NOISE);
	} else {		} else {
	phy_iq_est_t est[PHY_CORE_MAX];		phy_iq_est_t est[PHY_CORE_MAX];

drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_int.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1159,7 +1159,7 @@ extern void wlc_phy_table_write_nphy(phy_info_t *pi, u32, u32, u32,

	#define WLC_PHY_WAR_PR51571(pi) \		#define WLC_PHY_WAR_PR51571(pi) \
	if (((pi)->sh->bustype == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \		if (((pi)->sh->bustype == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \
	(void)R_REG((pi)->sh->osh, &(pi)->regs->maccontrol)		(void)R_REG(&(pi)->regs->maccontrol)

	extern void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, u8 caltype);		extern void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, u8 caltype);
	extern void wlc_phy_aci_reset_nphy(phy_info_t *pi);		extern void wlc_phy_aci_reset_nphy(phy_info_t *pi);

drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_lcn.c

+22 −22

Original line number	Original line	Diff line number	Diff line
	@@ -2100,7 +2100,7 @@ static void wlc_lcnphy_idle_tssi_est(wlc_phy_t *ppi)
	idleTssi = read_phy_reg(pi, 0x4ab);		idleTssi = read_phy_reg(pi, 0x4ab);
	suspend =		suspend =
	(0 ==		(0 ==
	(R_REG(pi->sh->osh, &((phy_info_t *) pi)->regs->maccontrol) &		(R_REG(&((phy_info_t *) pi)->regs->maccontrol) &
	MCTL_EN_MAC));		MCTL_EN_MAC));
	if (!suspend)		if (!suspend)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);
	@@ -2176,7 +2176,7 @@ static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode)
	for (i = 0; i < 14; i++)		for (i = 0; i < 14; i++)
	values_to_save[i] = read_phy_reg(pi, tempsense_phy_regs[i]);		values_to_save[i] = read_phy_reg(pi, tempsense_phy_regs[i]);
	suspend =		suspend =
	(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!suspend)		if (!suspend)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);
	save_txpwrCtrlEn = read_radio_reg(pi, 0x4a4);		save_txpwrCtrlEn = read_radio_reg(pi, 0x4a4);
	@@ -2303,7 +2303,7 @@ void WLBANDINITFN(wlc_lcnphy_tx_pwr_ctrl_init) (wlc_phy_t *ppi)
	phy_info_t pi = (phy_info_t ) ppi;		phy_info_t pi = (phy_info_t ) ppi;

	suspend =		suspend =
	(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!suspend)		if (!suspend)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);

	@@ -2989,7 +2989,7 @@ s16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode)
	if (mode == 1) {		if (mode == 1) {
	suspend =		suspend =
	(0 ==		(0 ==
	(R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!suspend)		if (!suspend)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);
	wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);		wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
	@@ -3036,7 +3036,7 @@ u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode)
	if (mode == 1) {		if (mode == 1) {
	suspend =		suspend =
	(0 ==		(0 ==
	(R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!suspend)		if (!suspend)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);
	wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);		wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
	@@ -3104,7 +3104,7 @@ s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode)
	if (mode == 1) {		if (mode == 1) {
	suspend =		suspend =
	(0 ==		(0 ==
	(R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!suspend)		if (!suspend)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);
	wlc_lcnphy_vbat_temp_sense_setup(pi, VBATSENSE);		wlc_lcnphy_vbat_temp_sense_setup(pi, VBATSENSE);
	@@ -3459,7 +3459,7 @@ static void wlc_lcnphy_glacial_timer_based_cal(phy_info_t *pi)
	u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);		u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
	phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;		phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
	suspend =		suspend =
	(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!suspend)		if (!suspend)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);
	wlc_lcnphy_deaf_mode(pi, true);		wlc_lcnphy_deaf_mode(pi, true);
	@@ -3501,7 +3501,7 @@ static void wlc_lcnphy_periodic_cal(phy_info_t *pi)
	index = pi_lcn->lcnphy_current_index;		index = pi_lcn->lcnphy_current_index;

	suspend =		suspend =
	(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!suspend) {		if (!suspend) {

	wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);		wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
	@@ -3859,15 +3859,15 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
	timer = 0;		timer = 0;
	old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);		old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);

	curval1 = R_REG(pi->sh->osh, &pi->regs->psm_corectlsts);		curval1 = R_REG(&pi->regs->psm_corectlsts);
	ptr[130] = 0;		ptr[130] = 0;
	W_REG(pi->sh->osh, &pi->regs->psm_corectlsts, ((1 << 6) \| curval1));		W_REG(&pi->regs->psm_corectlsts, ((1 << 6) \| curval1));

	W_REG(pi->sh->osh, &pi->regs->smpl_clct_strptr, 0x7E00);		W_REG(&pi->regs->smpl_clct_strptr, 0x7E00);
	W_REG(pi->sh->osh, &pi->regs->smpl_clct_stpptr, 0x8000);		W_REG(&pi->regs->smpl_clct_stpptr, 0x8000);
	udelay(20);		udelay(20);
	curval2 = R_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param);		curval2 = R_REG(&pi->regs->psm_phy_hdr_param);
	W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, curval2 \| 0x30);		W_REG(&pi->regs->psm_phy_hdr_param, curval2 \| 0x30);

	write_phy_reg(pi, 0x555, 0x0);		write_phy_reg(pi, 0x555, 0x0);
	write_phy_reg(pi, 0x5a6, 0x5);		write_phy_reg(pi, 0x5a6, 0x5);
	@@ -3884,19 +3884,19 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,

	sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);		sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
	write_phy_reg(pi, 0x6da, (u32) (sslpnCalibClkEnCtrl \| 0x2008));		write_phy_reg(pi, 0x6da, (u32) (sslpnCalibClkEnCtrl \| 0x2008));
	stpptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_stpptr);		stpptr = R_REG(&pi->regs->smpl_clct_stpptr);
	curptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_curptr);		curptr = R_REG(&pi->regs->smpl_clct_curptr);
	do {		do {
	udelay(10);		udelay(10);
	curptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_curptr);		curptr = R_REG(&pi->regs->smpl_clct_curptr);
	timer++;		timer++;
	} while ((curptr != stpptr) && (timer < 500));		} while ((curptr != stpptr) && (timer < 500));

	W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, 0x2);		W_REG(&pi->regs->psm_phy_hdr_param, 0x2);
	strptr = 0x7E00;		strptr = 0x7E00;
	W_REG(pi->sh->osh, &pi->regs->tplatewrptr, strptr);		W_REG(&pi->regs->tplatewrptr, strptr);
	while (strptr < 0x8000) {		while (strptr < 0x8000) {
	val = R_REG(pi->sh->osh, &pi->regs->tplatewrdata);		val = R_REG(&pi->regs->tplatewrdata);
	imag = ((val >> 16) & 0x3ff);		imag = ((val >> 16) & 0x3ff);
	real = ((val) & 0x3ff);		real = ((val) & 0x3ff);
	if (imag > 511) {		if (imag > 511) {
	@@ -3919,8 +3919,8 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
	}		}

	write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);		write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
	W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, curval2);		W_REG(&pi->regs->psm_phy_hdr_param, curval2);
	W_REG(pi->sh->osh, &pi->regs->psm_corectlsts, curval1);		W_REG(&pi->regs->psm_corectlsts, curval1);
	}		}

	static void wlc_lcnphy_tx_iqlo_soft_cal_full(phy_info_t *pi)		static void wlc_lcnphy_tx_iqlo_soft_cal_full(phy_info_t *pi)

drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_n.c

+25 −25

Original line number	Original line	Diff line number	Diff line
	@@ -14569,11 +14569,11 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi)
	&origidx, &intr_val);		&origidx, &intr_val);
	ASSERT(regs != NULL);		ASSERT(regs != NULL);

	d11_clk_ctl_st = R_REG(pi->sh->osh, &regs->clk_ctl_st);		d11_clk_ctl_st = R_REG(&regs->clk_ctl_st);
	AND_REG(pi->sh->osh, &regs->clk_ctl_st,		AND_REG(&regs->clk_ctl_st,
	~(CCS_FORCEHT \| CCS_HTAREQ));		~(CCS_FORCEHT \| CCS_HTAREQ));

	W_REG(pi->sh->osh, &regs->clk_ctl_st, d11_clk_ctl_st);		W_REG(&regs->clk_ctl_st, d11_clk_ctl_st);

	si_restore_core(pi->sh->sih, origidx, intr_val);		si_restore_core(pi->sh->sih, origidx, intr_val);
	}		}
	@@ -14964,7 +14964,7 @@ static void wlc_phy_resetcca_nphy(phy_info_t *pi)
	{		{
	u16 val;		u16 val;

	ASSERT(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		ASSERT(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));

	wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);		wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);

	@@ -15057,7 +15057,7 @@ void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask)
	return;		return;

	suspend =		suspend =
	(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!suspend)		if (!suspend)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);

	@@ -18983,28 +18983,28 @@ wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chanspec,
	val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;		val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
	if (CHSPEC_IS5G(chanspec) && !val) {		if (CHSPEC_IS5G(chanspec) && !val) {

	val = R_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param);		val = R_REG(&pi->regs->psm_phy_hdr_param);
	W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param,		W_REG(&pi->regs->psm_phy_hdr_param,
	(val \| MAC_PHY_FORCE_CLK));		(val \| MAC_PHY_FORCE_CLK));

	or_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),		or_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
	(BBCFG_RESETCCA \| BBCFG_RESETRX));		(BBCFG_RESETCCA \| BBCFG_RESETRX));

	W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, val);		W_REG(&pi->regs->psm_phy_hdr_param, val);

	or_phy_reg(pi, 0x09, NPHY_BandControl_currentBand);		or_phy_reg(pi, 0x09, NPHY_BandControl_currentBand);
	} else if (!CHSPEC_IS5G(chanspec) && val) {		} else if (!CHSPEC_IS5G(chanspec) && val) {

	and_phy_reg(pi, 0x09, ~NPHY_BandControl_currentBand);		and_phy_reg(pi, 0x09, ~NPHY_BandControl_currentBand);

	val = R_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param);		val = R_REG(&pi->regs->psm_phy_hdr_param);
	W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param,		W_REG(&pi->regs->psm_phy_hdr_param,
	(val \| MAC_PHY_FORCE_CLK));		(val \| MAC_PHY_FORCE_CLK));

	and_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),		and_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
	(u16) (~(BBCFG_RESETCCA \| BBCFG_RESETRX)));		(u16) (~(BBCFG_RESETCCA \| BBCFG_RESETRX)));

	W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, val);		W_REG(&pi->regs->psm_phy_hdr_param, val);
	}		}

	write_phy_reg(pi, 0x1ce, ci->PHY_BW1a);		write_phy_reg(pi, 0x1ce, ci->PHY_BW1a);
	@@ -19095,15 +19095,15 @@ wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chanspec,

	if (spuravoid == 1) {		if (spuravoid == 1) {

	W_REG(pi->sh->osh, &pi->regs->tsf_clk_frac_l,		W_REG(&pi->regs->tsf_clk_frac_l,
	0x5341);		0x5341);
	W_REG(pi->sh->osh, &pi->regs->tsf_clk_frac_h,		W_REG(&pi->regs->tsf_clk_frac_h,
	0x8);		0x8);
	} else {		} else {

	W_REG(pi->sh->osh, &pi->regs->tsf_clk_frac_l,		W_REG(&pi->regs->tsf_clk_frac_l,
	0x8889);		0x8889);
	W_REG(pi->sh->osh, &pi->regs->tsf_clk_frac_h,		W_REG(&pi->regs->tsf_clk_frac_h,
	0x8);		0x8);
	}		}
	}		}
	@@ -19609,13 +19609,13 @@ void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init)

	si_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);		si_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);

	mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);		mc = R_REG(&pi->regs->maccontrol);
	mc &= ~MCTL_GPOUT_SEL_MASK;		mc &= ~MCTL_GPOUT_SEL_MASK;
	W_REG(pi->sh->osh, &pi->regs->maccontrol, mc);		W_REG(&pi->regs->maccontrol, mc);

	OR_REG(pi->sh->osh, &pi->regs->psm_gpio_oe, mask);		OR_REG(&pi->regs->psm_gpio_oe, mask);

	AND_REG(pi->sh->osh, &pi->regs->psm_gpio_out, ~mask);		AND_REG(&pi->regs->psm_gpio_out, ~mask);

	if (lut_init) {		if (lut_init) {
	write_phy_reg(pi, 0xf8, 0x02d8);		write_phy_reg(pi, 0xf8, 0x02d8);
	@@ -19633,7 +19633,7 @@ u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val)

	if (D11REV_IS(pi->sh->corerev, 16)) {		if (D11REV_IS(pi->sh->corerev, 16)) {
	suspended =		suspended =
	(R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) ?		(R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) ?
	false : true;		false : true;
	if (!suspended)		if (!suspended)
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);
	@@ -27257,7 +27257,7 @@ static void wlc_phy_a4(phy_info_t *pi, bool full_cal)
	return;		return;

	phy_b3 =		phy_b3 =
	(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
	if (!phy_b3) {		if (!phy_b3) {
	wlapi_suspend_mac_and_wait(pi->sh->physhim);		wlapi_suspend_mac_and_wait(pi->sh->physhim);
	}		}
	@@ -28221,7 +28221,7 @@ void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi)

	if (D11REV_IS(pi->sh->corerev, 11) \|\| D11REV_IS(pi->sh->corerev, 12)) {		if (D11REV_IS(pi->sh->corerev, 11) \|\| D11REV_IS(pi->sh->corerev, 12)) {
	wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);		wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
	(void)R_REG(pi->sh->osh, &pi->regs->maccontrol);		(void)R_REG(&pi->regs->maccontrol);
	udelay(1);		udelay(1);
	}		}

	@@ -28492,7 +28492,7 @@ static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)

	if (D11REV_IS(pi->sh->corerev, 11) \|\| D11REV_IS(pi->sh->corerev, 12)) {		if (D11REV_IS(pi->sh->corerev, 11) \|\| D11REV_IS(pi->sh->corerev, 12)) {
	wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);		wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
	(void)R_REG(pi->sh->osh, &pi->regs->maccontrol);		(void)R_REG(&pi->regs->maccontrol);
	udelay(1);		udelay(1);
	}		}

	@@ -28649,7 +28649,7 @@ static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)

	if (D11REV_IS(pi->sh->corerev, 11) \|\| D11REV_IS(pi->sh->corerev, 12)) {		if (D11REV_IS(pi->sh->corerev, 11) \|\| D11REV_IS(pi->sh->corerev, 12)) {
	wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);		wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
	(void)R_REG(pi->sh->osh, &pi->regs->maccontrol);		(void)R_REG(&pi->regs->maccontrol);
	udelay(1);		udelay(1);
	}		}

	@@ -29194,7 +29194,7 @@ void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable)
	{		{
	u16 clip_off[] = { 0xffff, 0xffff };		u16 clip_off[] = { 0xffff, 0xffff };

	ASSERT(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));		ASSERT(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));

	if (enable) {		if (enable) {
	if (pi->nphy_deaf_count == 0) {		if (pi->nphy_deaf_count == 0) {