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Commit ff2e6d7e authored by Paul Mackerras's avatar Paul Mackerras
Browse files

powerpc: Fix goof in 6xx and POWER4 idle power-save functions 



This fixes a mistake I made when editing these functions - when I
took out the interrupt disabling code (because interrupts are now
disabled by the caller) I left the register that is used for the MSR
value to be used during doze/nap uninitialized.  This fixes it.

Also updated some of the comments in idle_power4.S and removed some
code that was copied over from idle_6xx.S but is no longer relevant
(we don't ever clear the CPU_FTR_CAN_NAP bit at runtime for POWER4).

Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 9618edab

arch/powerpc/kernel/idle_6xx.S

+2 −1
Original line number Diff line number Diff line
@@ -144,7 +144,8 @@ BEGIN_FTR_SECTION 
	DSSALL

	sync

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)

	ori	r7,r7,MSR_EE /* Could be ommited (already set) */

	mfmsr	r7

	ori	r7,r7,MSR_EE

	oris	r7,r7,MSR_POW@h

	sync

	isync

arch/powerpc/kernel/idle_power4.S

+3 −20
Original line number Diff line number Diff line 
/*

 *  This file contains the power_save function for 6xx & 7xxx CPUs

 *  rewritten in assembler

 *

 *  Warning ! This code assumes that if your machine has a 750fx

 *  it will have PLL 1 set to low speed mode (used during NAP/DOZE).

 *  if this is not the case some additional changes will have to

 *  be done to check a runtime var (a bit like powersave-nap)

 *  This file contains the power_save function for 970-family CPUs.

 *

 *  This program is free software; you can redistribute it and/or

 *  modify it under the terms of the GNU General Public License
@@ -26,23 +20,10 @@ 


	.text



/*

 * Here is the power_save_6xx function. This could eventually be

 * split into several functions & changing the function pointer

 * depending on the various features.

 */

_GLOBAL(power4_idle)

BEGIN_FTR_SECTION

	blr

END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)

	/* We must dynamically check for the NAP feature as it

	 * can be cleared by CPU init after the fixups are done

	 */

	LOAD_REG_ADDRBASE(r3,cur_cpu_spec)

	ld	r4,ADDROFF(cur_cpu_spec)(r3)

	ld	r4,CPU_SPEC_FEATURES(r4)

	andi.	r0,r4,CPU_FTR_CAN_NAP

	beqlr

	/* Now check if user or arch enabled NAP mode */

	LOAD_REG_ADDRBASE(r3,powersave_nap)

	lwz	r4,ADDROFF(powersave_nap)(r3)
@@ -54,6 +35,8 @@ BEGIN_FTR_SECTION 
	DSSALL

	sync

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)

	mfmsr	r7

	ori	r7,r7,MSR_EE

	oris	r7,r7,MSR_POW@h

	sync

	isync