Merge "ARM: dts: msm: Add the clock nodes on SDM845 v2" (ff08dde7) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/clock/qcom,camcc.txt

+1 −1

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		@@ -2,7 +2,7 @@ Qualcomm Technologies Camera Clock & Reset Controller Binding
		----------------------------------------------------

		Required properties :
		- compatible : shall contain "qcom,cam_cc-sdm845"
		- compatible : shall contain "qcom,cam_cc-sdm845" or "qcom,cam_cc-sdm845-v2"
		- reg : shall contain base register location and length
		- reg-names: names of registers listed in the same order as in
		the reg property.

+1 −1

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		@@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding
		----------------------------------------------------

		Required properties :
		- compatible : shall contain "qcom,dispcc-sdm845".
		- compatible : shall contain "qcom,dispcc-sdm845" or "qcom,dispcc-sdm845-v2".
		- reg : shall contain base register location and length.
		- reg-names: names of registers listed in the same order as in
		the reg property.

+1 −0

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		@@ -17,6 +17,7 @@ Required properties :
		"qcom,gcc-msm8996"
		"qcom,gcc-mdm9615"
		"qcom,gcc-sdm845"
		"qcom,gcc-sdm845-v2"
		"qcom,debugcc-sdm845"

		- reg : shall contain base register location and length

+5 −4

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		@@ -2,12 +2,13 @@ Qualcomm Technologies Video Clock & Reset Controller Binding
		----------------------------------------------------

		Required properties :
		- compatible : shall contain "qcom,video_cc-sdm845"
		- reg : shall contain base register location and length
		- compatible : shall contain "qcom,video_cc-sdm845" or
		"qcom,video_cc-sdm845-v2".
		- reg : shall contain base register location and length.
		- reg-names: names of registers listed in the same order as in
		the reg property.
		- #clock-cells : shall contain 1
		- #reset-cells : shall contain 1
		- #clock-cells : shall contain 1.
		- #reset-cells : shall contain 1.

		Optional properties :
		- vdd_<rail>-supply: The logic rail supply.

+16 −0

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		@@ -20,3 +20,19 @@
		&spmi_debug_bus {
		status = "ok";
		};

		&clock_gcc {
		compatible = "qcom,gcc-sdm845-v2";
		};

		&clock_camcc {
		compatible = "qcom,cam_cc-sdm845-v2";
		};

		&clock_dispcc {
		compatible = "qcom,dispcc-sdm845-v2";
		};

		&clock_videocc {
		compatible = "qcom,video_cc-sdm845-v2";
		};