Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fdf5d357 authored by Alex Dai's avatar Alex Dai Committed by Daniel Vetter
Browse files

drm/i915: Debugfs interface to read GuC load status 



The new node provides access to the status of the GuC-specific loader;
also the scratch registers used for communication between the i915
driver and the GuC firmware.

v2:
    Changes to output formats per Chris Wilson's suggestions

v6:
    Rebased

Issue: VIZ-4884
Signed-off-by: default avatarAlex Dai <yu.dai@intel.com>
Signed-off-by: default avatarDave Gordon <david.s.gordon@intel.com>
Reviewed-by: default avatarTom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 33a732f4

drivers/gpu/drm/i915/i915_debugfs.c

+39 −0
Original line number Diff line number Diff line
@@ -2374,6 +2374,44 @@ static int i915_llc(struct seq_file *m, void *data) 
	return 0;

}



static int i915_guc_load_status_info(struct seq_file *m, void *data)

{

	struct drm_info_node *node = m->private;

	struct drm_i915_private *dev_priv = node->minor->dev->dev_private;

	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;

	u32 tmp, i;



	if (!HAS_GUC_UCODE(dev_priv->dev))

		return 0;



	seq_printf(m, "GuC firmware status:\n");

	seq_printf(m, "\tpath: %s\n",

		guc_fw->guc_fw_path);

	seq_printf(m, "\tfetch: %s\n",

		intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));

	seq_printf(m, "\tload: %s\n",

		intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));

	seq_printf(m, "\tversion wanted: %d.%d\n",

		guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);

	seq_printf(m, "\tversion found: %d.%d\n",

		guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);



	tmp = I915_READ(GUC_STATUS);



	seq_printf(m, "\nGuC status 0x%08x:\n", tmp);

	seq_printf(m, "\tBootrom status = 0x%x\n",

		(tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);

	seq_printf(m, "\tuKernel status = 0x%x\n",

		(tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);

	seq_printf(m, "\tMIA Core status = 0x%x\n",

		(tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);

	seq_puts(m, "\nScratch registers:\n");

	for (i = 0; i < 16; i++)

		seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));



	return 0;

}



static int i915_edp_psr_status(struct seq_file *m, void *data)

{

	struct drm_info_node *node = m->private;
@@ -5033,6 +5071,7 @@ static const struct drm_info_list i915_debugfs_list[] = { 
	{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},

	{"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},

	{"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},

	{"i915_guc_load_status", i915_guc_load_status_info, 0},

	{"i915_frequency_info", i915_frequency_info, 0},

	{"i915_hangcheck_info", i915_hangcheck_info, 0},

	{"i915_drpc_info", i915_drpc_info, 0},