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Commit fde97822 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Add macros to encode processor revisions. 



Older processors used to encode processor version and revision in two
4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
have switched to use the 8-bits as 3:3:2 bitfield with the last field as
the patch number.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 075c733e

include/asm-mips/cpu.h

+11 −0
Original line number Diff line number Diff line
@@ -124,6 +124,17 @@ 
#define PRID_REV_VR4181A	0x0070	/* Same as VR4122 */

#define PRID_REV_VR4130		0x0080



/*

 * Older processors used to encode processor version and revision in two

 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores

 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as

 * the patch number.  *ARGH*

 */

#define PRID_REV_ENCODE_44(ver, rev)					\

	((ver) << 4 | (rev))

#define PRID_REV_ENCODE_332(ver, rev, patch)				\

	((ver) << 5 | (rev) << 2 | (patch))



/*

 * FPU implementation/revision register (CP1 control register 0).

 *