Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fda052b0 authored by Mark Brown's avatar Mark Brown
Browse files

Merge remote-tracking branches 'spi/topic/sirf', 'spi/topic/spidev' and... 

Merge remote-tracking branches 'spi/topic/sirf', 'spi/topic/spidev' and 'spi/topic/zynq' into spi-next
parents b9e2c097 5bcc3b0b 99472cc0 2c05136c

Documentation/devicetree/bindings/spi/spi-sirf.txt

+2 −1
Original line number Original line Diff line number Diff line 
* CSR SiRFprimaII Serial Peripheral Interface

* CSR SiRFprimaII Serial Peripheral Interface





Required properties:

Required properties:

- compatible : Should be "sirf,prima2-spi"

- compatible : Should be "sirf,prima2-spi", "sirf,prima2-usp"

               or "sirf,atlas7-usp"

- reg : Offset and length of the register set for the device

- reg : Offset and length of the register set for the device

- interrupts : Should contain SPI interrupt

- interrupts : Should contain SPI interrupt

- resets: phandle to the reset controller asserting this device in

- resets: phandle to the reset controller asserting this device in

Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt

0 → 100644
+26 −0
Original line number Original line Diff line number Diff line 
Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings

-------------------------------------------------------------------



Required properties:

- compatible		: Should be "xlnx,zynqmp-qspi-1.0".

- reg			: Physical base address and size of GQSPI registers map.

- interrupts		: Property with a value describing the interrupt

			  number.

- interrupt-parent	: Must be core interrupt controller.

- clock-names		: List of input clock names - "ref_clk", "pclk"

			  (See clock bindings for details).

- clocks		: Clock phandles (see clock bindings for details).



Optional properties:

- num-cs		: Number of chip selects used.



Example:

	qspi: spi@ff0f0000 {

		compatible = "xlnx,zynqmp-qspi-1.0";

		clock-names = "ref_clk", "pclk";

		clocks = <&misc_clk &misc_clk>;

		interrupts = <0 15 4>;

		interrupt-parent = <&gic>;

		num-cs = <1>;

		reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;

	};

drivers/spi/Kconfig

+6 −0
Original line number Original line Diff line number Diff line
@@ -610,6 +610,12 @@ config SPI_XTENSA_XTFPGA 
	  16 bit words in SPI mode 0, automatically asserting CS on transfer

	  16 bit words in SPI mode 0, automatically asserting CS on transfer

	  start and deasserting on end.

	  start and deasserting on end.





config SPI_ZYNQMP_GQSPI

	tristate "Xilinx ZynqMP GQSPI controller"

	depends on SPI_MASTER

	help

	  Enables Xilinx GQSPI controller driver for Zynq UltraScale+ MPSoC.



config SPI_NUC900

config SPI_NUC900

	tristate "Nuvoton NUC900 series SPI"

	tristate "Nuvoton NUC900 series SPI"

	depends on ARCH_W90X900

	depends on ARCH_W90X900

drivers/spi/Makefile

+1 −0
Original line number Original line Diff line number Diff line
@@ -89,3 +89,4 @@ obj-$(CONFIG_SPI_TXX9) += spi-txx9.o 
obj-$(CONFIG_SPI_XCOMM)		+= spi-xcomm.o

obj-$(CONFIG_SPI_XCOMM)		+= spi-xcomm.o

obj-$(CONFIG_SPI_XILINX)		+= spi-xilinx.o

obj-$(CONFIG_SPI_XILINX)		+= spi-xilinx.o

obj-$(CONFIG_SPI_XTENSA_XTFPGA)		+= spi-xtensa-xtfpga.o

obj-$(CONFIG_SPI_XTENSA_XTFPGA)		+= spi-xtensa-xtfpga.o

obj-$(CONFIG_SPI_ZYNQMP_GQSPI)		+= spi-zynqmp-gqspi.o

drivers/spi/spi-sirf.c

+639 −238

File changed.

Preview size limit exceeded, changes collapsed.