Merge "ufs: snapshot of UFS controller & PHY driver" into msm-4.9

contain a phandle reference to UFS PHY node.

Required properties:

- compatible        : compatible list, contains one of the following:

- compatible        : compatible list, contains one of the following

		      according to the relevant phy in use:

		      "qcom,ufs-phy-qmp-14nm"

		      "qcom,ufs-phy-qmp-v3"

		      "qcom,ufs-phy-qrbtc-sdm845"

according to the relevant phy in use.

		      "qcom,ufs-phy-qmp-v3-660"

- reg               : should contain PHY register address space (mandatory),

- reg-names         : indicates various resources passed to driver (via reg proptery) by name.

                      Required "reg-names" is "phy_mem".

Optional properties:

- vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply

- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply

- vddp-ref-clk-supply   : phandle to UFS device ref_clk pad power supply

- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply

- vddp-ref-clk-always-on : specifies if this supply needs to be kept always on

- qcom,disable-lpm : disable various LPM mechanisms in UFS for platform compatibility

  (limit link to PWM Gear-1, 1-lane slow mode; disable hibernate, and avoid suspend/resume)

- reg               : <registers mapping>

		      first entry should contain UFS host controller register address space (mandatory),

                      second entry is the device ref. clock control register map (optional).

- reset             : reset specifier pair consists of phandle for the reset provider

                      and reset lines used by this controller.

- reset-names       : reset signal name strings sorted in the same order as the resets property.

Optional properties:

- phys                  : phandle to UFS PHY node

- lanes-per-direction:	number of lanes available per direction - either 1 or 2.

			Note that it is assume same number of lanes is used both directions at once.

			If not specified, default is 2 lanes per direction.

- pinctrl-names, pinctrl-0, pinctrl-1,.. pinctrl-n: Refer to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt"

			for these optional properties

- limit-tx-hs-gear	: Specify the max. limit on the TX HS gear.

			  Valid range: 1-3. 1 => HS-G1, 2 => HS-G2, 3 => HS-G3

- limit-rx-hs-gear	: Specify the max. limit on the RX HS gear. Refer "limit-tx-hs-gear" for expected values.

		clocks = <&core 0>, <&ref 0>, <&iface 0>;

		clock-names = "core_clk", "ref_clk", "iface_clk";

		freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;

		resets = <clock_gcc GCC_UFS_BCR>;

		reset-names = "core_reset";

		phys = <&ufsphy1>;

		phy-names = "ufsphy";

		rpm-level = <3>;

- qcom,pm-qos-default-cpu:		PM QoS voting is based on the cpu associated with each IO request by the block layer.

					This defined the default cpu used for PM QoS voting in case a specific cpu value is not available.

- qcom,vddp-ref-clk-supply	 : reference clock to ufs device. Controlled by the host driver.

- qcom,vddp-ref-clk-max-microamp : specifies max. load that can be drawn for

				   ref-clk supply.

Example:

	ufshc@0xfc598000 {

		...

obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-14nm.o

obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-v3.o

obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qrbtc-sdm845.o

obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-v3-660.o

obj-$(CONFIG_PHY_TUSB1210)		+= phy-tusb1210.o

obj-$(CONFIG_PHY_BRCM_SATA)		+= phy-brcm-sata.o

obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o

 * and writes to QSERDES_RX_SIGDET_CNTRL attribute

 * @configure_lpm: pointer to a function that configures the phy

 * for low power mode.

 * @dbg_register_dump: pointer to a function that dumps phy registers for debug.

 */

struct ufs_qcom_phy_specific_ops {

	int (*calibrate_phy)(struct ufs_qcom_phy *phy, bool is_rate_B);

	void (*ctrl_rx_linecfg)(struct ufs_qcom_phy *phy, bool ctrl);

	void (*power_control)(struct ufs_qcom_phy *phy, bool val);

	int (*configure_lpm)(struct ufs_qcom_phy *phy, bool enable);

	void (*dbg_register_dump)(struct ufs_qcom_phy *phy);

};

struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy);

void ufs_qcom_phy_write_tbl(struct ufs_qcom_phy *ufs_qcom_phy,

				struct ufs_qcom_phy_calibration *tbl,

				int tbl_size);

void ufs_qcom_phy_dump_regs(struct ufs_qcom_phy *phy,

			    int offset, int len, char *prefix);

#endif

/*

 * Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */

#include "phy-qcom-ufs-qmp-v3-660.h"

#define UFS_PHY_NAME "ufs_phy_qmp_v3_660"

static

int ufs_qcom_phy_qmp_v3_660_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,

					bool is_rate_B)

{

	int err;

	int tbl_size_A, tbl_size_B;

	struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;

	u8 major = ufs_qcom_phy->host_ctrl_rev_major;

	u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;

	u16 step = ufs_qcom_phy->host_ctrl_rev_step;

	tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);

	tbl_B = phy_cal_table_rate_B;

	if ((major == 0x3) && (minor == 0x001) && (step == 0x001)) {

		tbl_A = phy_cal_table_rate_A_3_1_1;

		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_3_1_1);

	} else {

		dev_err(ufs_qcom_phy->dev,

			"%s: Unknown UFS-PHY version (major 0x%x minor 0x%x step 0x%x), no calibration values\n",

			__func__, major, minor, step);

		err = -ENODEV;

		goto out;

	}

	err = ufs_qcom_phy_calibrate(ufs_qcom_phy,

				     tbl_A, tbl_size_A,

				     tbl_B, tbl_size_B,

				     is_rate_B);

	if (err)

		dev_err(ufs_qcom_phy->dev,

			"%s: ufs_qcom_phy_calibrate() failed %d\n",

			__func__, err);

out:

	return err;

}

static int ufs_qcom_phy_qmp_v3_660_init(struct phy *generic_phy)

{

	struct ufs_qcom_phy_qmp_v3_660 *phy = phy_get_drvdata(generic_phy);

	struct ufs_qcom_phy *phy_common = &phy->common_cfg;

	int err;

	err = ufs_qcom_phy_init_clks(generic_phy, phy_common);

	if (err) {

		dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",

			__func__, err);

		goto out;

	}

	err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);

	if (err) {

		dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",

			__func__, err);

		goto out;

	}

out:

	return err;

}

static

void ufs_qcom_phy_qmp_v3_660_power_control(struct ufs_qcom_phy *phy,

					 bool power_ctrl)

{

	if (!power_ctrl) {

		/* apply analog power collapse */

		writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);

		/*

		 * Make sure that PHY knows its analog rail is going to be

		 * powered OFF.

		 */

		mb();

	} else {

		/* bring PHY out of analog power collapse */

		writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);

		/*

		 * Before any transactions involving PHY, ensure PHY knows

		 * that it's analog rail is powered ON.

		 */

		mb();

	}

}

static inline

void ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable(struct ufs_qcom_phy *phy,

						   u32 val)

{

	/*

	 * v3 PHY does not have TX_LANE_ENABLE register.

	 * Implement this function so as not to propagate error to caller.

	 */

}

static

void ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg(struct ufs_qcom_phy *phy,

						bool ctrl)

{

	u32 temp;

	temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE);

	if (ctrl) /* enable RX LineCfg */

		temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT;

	else /* disable RX LineCfg */

		temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT;

	writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE);

	/* Make sure that RX LineCfg config applied before we return */

	mb();

}

static inline void ufs_qcom_phy_qmp_v3_660_start_serdes(

					struct ufs_qcom_phy *phy)

{

	u32 tmp;

	tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);

	tmp &= ~MASK_SERDES_START;

	tmp |= (1 << OFFSET_SERDES_START);

	writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);

	/* Ensure register value is committed */

	mb();

}

static int ufs_qcom_phy_qmp_v3_660_is_pcs_ready(

				struct ufs_qcom_phy *phy_common)

{

	int err = 0;

	u32 val;

	err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,

		val, (val & MASK_PCS_READY), 10, 1000000);

	if (err)

		dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",

			__func__, err);

	return err;

}

static void ufs_qcom_phy_qmp_v3_660_dbg_register_dump(

					struct ufs_qcom_phy *phy)

{

	ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE,

					"PHY QSERDES COM Registers ");

	ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE,

					"PHY Registers ");

	ufs_qcom_phy_dump_regs(phy, RX_BASE, RX_SIZE,

					"PHY RX0 Registers ");

	ufs_qcom_phy_dump_regs(phy, TX_BASE, TX_SIZE,

					"PHY TX0 Registers ");

}

struct phy_ops ufs_qcom_phy_qmp_v3_660_phy_ops = {

	.init		= ufs_qcom_phy_qmp_v3_660_init,

	.exit		= ufs_qcom_phy_exit,

	.power_on	= ufs_qcom_phy_power_on,

	.power_off	= ufs_qcom_phy_power_off,

	.owner		= THIS_MODULE,

};

struct ufs_qcom_phy_specific_ops phy_v3_660_ops = {

	.calibrate_phy		= ufs_qcom_phy_qmp_v3_660_phy_calibrate,

	.start_serdes		= ufs_qcom_phy_qmp_v3_660_start_serdes,

	.is_physical_coding_sublayer_ready =

				ufs_qcom_phy_qmp_v3_660_is_pcs_ready,

	.set_tx_lane_enable	= ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable,

	.ctrl_rx_linecfg	= ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg,

	.power_control		= ufs_qcom_phy_qmp_v3_660_power_control,

	.dbg_register_dump	= ufs_qcom_phy_qmp_v3_660_dbg_register_dump,

};

static int ufs_qcom_phy_qmp_v3_660_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct phy *generic_phy;

	struct ufs_qcom_phy_qmp_v3_660 *phy;

	int err = 0;

	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);

	if (!phy) {

		err = -ENOMEM;

		goto out;

	}

	generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,

				&ufs_qcom_phy_qmp_v3_660_phy_ops,

				&phy_v3_660_ops);

	if (!generic_phy) {

		dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",

			__func__);

		err = -EIO;

		goto out;

	}

	phy_set_drvdata(generic_phy, phy);

	strlcpy(phy->common_cfg.name, UFS_PHY_NAME,

		sizeof(phy->common_cfg.name));

out:

	return err;

}

static int ufs_qcom_phy_qmp_v3_660_remove(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct phy *generic_phy = to_phy(dev);

	struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);

	int err = 0;

	err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);

	if (err)

		dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",

			__func__, err);

	return err;

}

static const struct of_device_id ufs_qcom_phy_qmp_v3_660_of_match[] = {

	{.compatible = "qcom,ufs-phy-qmp-v3-660"},

	{},

};

MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_660_of_match);

static struct platform_driver ufs_qcom_phy_qmp_v3_660_driver = {

	.probe = ufs_qcom_phy_qmp_v3_660_probe,

	.remove = ufs_qcom_phy_qmp_v3_660_remove,

	.driver = {

		.of_match_table = ufs_qcom_phy_qmp_v3_660_of_match,

		.name = "ufs_qcom_phy_qmp_v3_660",

		.owner = THIS_MODULE,

	},

};

module_platform_driver(ufs_qcom_phy_qmp_v3_660_driver);

MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 660");

MODULE_LICENSE("GPL v2");