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Commit fd2b5d5f authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: clk-rpmh: remove LN_BB_CLK1 as votable clock" into msm-4.9

parents 2f2f6e50 918ffada

arch/arm64/boot/dts/qcom/sdm845.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -1005,7 +1005,7 @@ 
		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

		clocks = <&clock_rpmh RPMH_LN_BB_CLK1>,

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;
@@ -1039,7 +1039,7 @@ 
			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&clock_rpmh RPMH_LN_BB_CLK1>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
@@ -1125,7 +1125,7 @@ 
		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

		clocks = <&clock_rpmh RPMH_LN_BB_CLK1>,

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_CARD_CLKREF_CLK>,

			<&clock_gcc GCC_UFS_CARD_PHY_AUX_CLK>;
@@ -1158,7 +1158,7 @@ 
			<&clock_gcc GCC_UFS_CARD_AHB_CLK>,

			<&clock_gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,

			<&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>,

			<&clock_rpmh RPMH_LN_BB_CLK1>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>;

		freq-table-hz =

drivers/clk/qcom/clk-rpmh.c

+0 −5
Original line number Diff line number Diff line
@@ -277,9 +277,6 @@ DEFINE_RSC_TYPE(disp_rsc, "display", true); 
DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 0x0,

		    &apps_rsc, 19200000, CLK_RPMH_APPS_RSC_STATE_MASK,

		    CLK_RPMH_APPS_RSC_AO_STATE_MASK);

DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", &apps_rsc,

		    19200000, CLK_RPMH_APPS_RSC_STATE_MASK,

		    CLK_RPMH_APPS_RSC_AO_STATE_MASK);

DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", &apps_rsc,

		    19200000, CLK_RPMH_APPS_RSC_STATE_MASK,

		    CLK_RPMH_APPS_RSC_AO_STATE_MASK);
@@ -299,8 +296,6 @@ DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", &apps_rsc, 
static struct clk_hw *sdm845_rpmh_clocks[] = {

	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,

	[RPMH_CXO_CLK_A]	= &sdm845_bi_tcxo_ao.hw,

	[RPMH_LN_BB_CLK1]	= &sdm845_ln_bb_clk1.hw,

	[RPMH_LN_BB_CLK1_A]	= &sdm845_ln_bb_clk1_ao.hw,

	[RPMH_LN_BB_CLK2]	= &sdm845_ln_bb_clk2.hw,

	[RPMH_LN_BB_CLK2_A]	= &sdm845_ln_bb_clk2_ao.hw,

	[RPMH_LN_BB_CLK3]	= &sdm845_ln_bb_clk3.hw,

include/dt-bindings/clock/qcom,rpmh.h

+12 −14
Original line number Diff line number Diff line
@@ -17,19 +17,17 @@ 
/* RPMh controlled clocks */

#define RPMH_CXO_CLK						0

#define RPMH_CXO_CLK_A						1

#define RPMH_LN_BB_CLK1						2

#define RPMH_LN_BB_CLK1_A					3

#define RPMH_LN_BB_CLK2						4

#define RPMH_LN_BB_CLK2_A					5

#define RPMH_LN_BB_CLK3						6

#define RPMH_LN_BB_CLK3_A					7

#define RPMH_RF_CLK1						8

#define RPMH_RF_CLK1_A						9

#define RPMH_RF_CLK2						10

#define RPMH_RF_CLK2_A						11

#define RPMH_RF_CLK3						12

#define RPMH_RF_CLK3_A						13

#define RPMH_QDSS_CLK						14

#define RPMH_QDSS_A_CLK						15

#define RPMH_LN_BB_CLK2						2

#define RPMH_LN_BB_CLK2_A					3

#define RPMH_LN_BB_CLK3						4

#define RPMH_LN_BB_CLK3_A					5

#define RPMH_RF_CLK1						6

#define RPMH_RF_CLK1_A						7

#define RPMH_RF_CLK2						8

#define RPMH_RF_CLK2_A						9

#define RPMH_RF_CLK3						10

#define RPMH_RF_CLK3_A						11

#define RPMH_QDSS_CLK						12

#define RPMH_QDSS_A_CLK						13



#endif