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Commit fd166a18 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/disp: cosmetic changes 



This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent e2f1cf25

drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h

+1 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
#include <core/event.h>



struct nvkm_disp {

	struct nvkm_engine base;

	struct nvkm_engine engine;



	struct list_head outp;

drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c

+3 −3
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ _nvkm_disp_fini(struct nvkm_object *object, bool suspend) 
			goto fail_outp;

	}



	return nvkm_engine_fini(&disp->base, suspend);

	return nvkm_engine_fini(&disp->engine, suspend);



fail_outp:

	list_for_each_entry_continue_reverse(outp, &disp->outp, head) {
@@ -144,7 +144,7 @@ _nvkm_disp_init(struct nvkm_object *object) 
	struct nvkm_output *outp;

	int ret;



	ret = nvkm_engine_init(&disp->base);

	ret = nvkm_engine_init(&disp->engine);

	if (ret)

		return ret;
@@ -179,7 +179,7 @@ _nvkm_disp_dtor(struct nvkm_object *object) 
		}

	}



	nvkm_engine_destroy(&disp->base);

	nvkm_engine_destroy(&disp->engine);

}



int

drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c

+10 −10
Original line number Diff line number Diff line
@@ -53,9 +53,9 @@ nv50_dac_power(NV50_DISP_MTHD_V1) 
	} else

		return ret;



	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);

	nv_mask(priv, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);

	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);

	nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);

	nv_mask(disp, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);

	nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);

	return 0;

}
@@ -79,18 +79,18 @@ nv50_dac_sense(NV50_DISP_MTHD_V1) 
	} else

		return ret;



	nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);

	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);

	nv_mask(disp, 0x61a004 + doff, 0x807f0000, 0x80150000);

	nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);



	nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);

	nv_wr32(disp, 0x61a00c + doff, 0x00100000 | loadval);

	mdelay(9);

	udelay(500);

	loadval = nv_mask(priv, 0x61a00c + doff, 0xffffffff, 0x00000000);

	loadval = nv_mask(disp, 0x61a00c + doff, 0xffffffff, 0x00000000);



	nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);

	nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);

	nv_mask(disp, 0x61a004 + doff, 0x807f0000, 0x80550000);

	nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);



	nv_debug(priv, "DAC%d sense: 0x%08x\n", outp->or, loadval);

	nv_debug(disp, "DAC%d sense: 0x%08x\n", outp->or, loadval);

	if (!(loadval & 0x80000000))

		return -ETIMEDOUT;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c

+4 −4
Original line number Diff line number Diff line
@@ -322,7 +322,7 @@ void 
nvkm_dp_train(struct work_struct *w)

{

	struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work);

	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);

	struct nv50_disp *disp = (void *)nvkm_disp(outp);

	const struct dp_rates *cfg = nvkm_dp_rates;

	struct dp_state _dp = {

		.outp = outp,
@@ -330,11 +330,11 @@ nvkm_dp_train(struct work_struct *w) 
	u32 datarate = 0;

	int ret;



	if (!outp->base.info.location && priv->sor.magic)

		priv->sor.magic(&outp->base);

	if (!outp->base.info.location && disp->sor.magic)

		disp->sor.magic(&outp->base);



	/* bring capabilities within encoder limits */

	if (nv_mclass(priv) < GF110_DISP)

	if (nv_mclass(disp) < GF110_DISP)

		outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;

	if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) {

		outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;

drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

+18 −18
Original line number Diff line number Diff line
@@ -223,33 +223,33 @@ g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
	      struct nvkm_oclass *oclass, void *data, u32 size,

	      struct nvkm_object **pobject)

{

	struct nv50_disp_priv *priv;

	struct nv50_disp *disp;

	int ret;



	ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",

			       "display", &priv);

	*pobject = nv_object(priv);

			       "display", &disp);

	*pobject = nv_object(disp);

	if (ret)

		return ret;



	ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);

	ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);

	if (ret)

		return ret;



	nv_engine(priv)->sclass = g84_disp_main_oclass;

	nv_engine(priv)->cclass = &nv50_disp_cclass;

	nv_subdev(priv)->intr = nv50_disp_intr;

	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);

	priv->sclass = g84_disp_sclass;

	priv->head.nr = 2;

	priv->dac.nr = 3;

	priv->sor.nr = 2;

	priv->pior.nr = 3;

	priv->dac.power = nv50_dac_power;

	priv->dac.sense = nv50_dac_sense;

	priv->sor.power = nv50_sor_power;

	priv->sor.hdmi = g84_hdmi_ctrl;

	priv->pior.power = nv50_pior_power;

	nv_engine(disp)->sclass = g84_disp_main_oclass;

	nv_engine(disp)->cclass = &nv50_disp_cclass;

	nv_subdev(disp)->intr = nv50_disp_intr;

	INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);

	disp->sclass = g84_disp_sclass;

	disp->head.nr = 2;

	disp->dac.nr = 3;

	disp->sor.nr = 2;

	disp->pior.nr = 3;

	disp->dac.power = nv50_dac_power;

	disp->dac.sense = nv50_dac_sense;

	disp->sor.power = nv50_sor_power;

	disp->sor.hdmi = g84_hdmi_ctrl;

	disp->pior.power = nv50_pior_power;

	return 0;

}