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Commit fc839753 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'imx-drm-next-2015-01-09' of git://git.pengutronix.de/git/pza/linux into drm-next 

imx-drm mode fixup support, imx-hdmi bridge conversion and imx-drm cleanup

- Implement mode_fixup for a DI vertical timing limitation
- Use generic DRM OF helpers in DRM core
- Convert imx-hdmi to dw_hdmi drm_bridge and add rockchip
  driver
- Add DC use counter to fix multi-display support
- Simplify handling of DI clock flags
- A few small fixes and cleanup

* tag 'imx-drm-next-2015-01-09' of git://git.pengutronix.de/git/pza/linux: (26 commits)
  imx-drm: core: handling of DI clock flags to ipu_crtc_mode_set()
  gpu: ipu-di: Switch to DIV_ROUND_CLOSEST for DI clock divider calc
  gpu: ipu-v3: Use videomode in struct ipu_di_signal_cfg
  imx-drm: encoder prepare/mode_set must use adjusted mode
  imx-drm: ipuv3-crtc: Implement mode_fixup
  drm_modes: add drm_display_mode_to_videomode
  gpu: ipu-di: remove some non-functional code
  gpu: ipu-di: Add ipu_di_adjust_videomode()
  drm: rockchip: export functions needed by rockchip dw_hdmi bridge driver
  drm: bridge/dw_hdmi: request interrupt only after initializing the mutes
  drm: bridge/dw_hdmi: add rockchip rk3288 support
  dt-bindings: Add documentation for rockchip dw hdmi
  drm: bridge/dw_hdmi: add function dw_hdmi_phy_enable_spare
  drm: bridge/dw_hdmi: clear i2cmphy_stat0 reg in hdmi_phy_wait_i2c_done
  drm: bridge/dw_hdmi: add mode_valid support
  drm: bridge/dw_hdmi: add support for multi-byte register width access
  dt-bindings: add document for dw_hdmi
  drm: imx: imx-hdmi: move imx-hdmi to bridge/dw_hdmi
  drm: imx: imx-hdmi: split phy configuration to platform driver
  drm: imx: imx-hdmi: convert imx-hdmi to drm_bridge mode
  ...
parents b2eb0489 d50141d8

Documentation/devicetree/bindings/drm/bridge/dw_hdmi.txt

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DesignWare HDMI bridge bindings



Required properties:

- compatible: platform specific such as:

   * "snps,dw-hdmi-tx"

   * "fsl,imx6q-hdmi"

   * "fsl,imx6dl-hdmi"

   * "rockchip,rk3288-dw-hdmi"

- reg: Physical base address and length of the controller's registers.

- interrupts: The HDMI interrupt number

- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,

  as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,

  the clocks are soc specific, the clock-names should be "iahb", "isfr"

-port@[X]: SoC specific port nodes with endpoint definitions as defined

   in Documentation/devicetree/bindings/media/video-interfaces.txt,

   please refer to the SoC specific binding document:

    * Documentation/devicetree/bindings/drm/imx/hdmi.txt

    * Documentation/devicetree/bindings/video/dw_hdmi-rockchip.txt



Optional properties

- reg-io-width: the width of the reg:1,4, default set to 1 if not present

- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing

- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"



Example:

	hdmi: hdmi@0120000 {

		compatible = "fsl,imx6q-hdmi";

		reg = <0x00120000 0x9000>;

		interrupts = <0 115 0x04>;

		gpr = <&gpr>;

		clocks = <&clks 123>, <&clks 124>;

		clock-names = "iahb", "isfr";

		ddc-i2c-bus = <&i2c2>;



		port@0 {

			reg = <0>;



			hdmi_mux_0: endpoint {

				remote-endpoint = <&ipu1_di0_hdmi>;

			};

		};



		port@1 {

			reg = <1>;



			hdmi_mux_1: endpoint {

				remote-endpoint = <&ipu1_di1_hdmi>;

			};

		};

	};

Documentation/devicetree/bindings/video/dw_hdmi-rockchip.txt

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Rockchip specific extensions to the Synopsys Designware HDMI

================================



Required properties:

- compatible: "rockchip,rk3288-dw-hdmi";

- reg: Physical base address and length of the controller's registers.

- clocks: phandle to hdmi iahb and isfr clocks.

- clock-names: should be "iahb" "isfr"

- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.

- interrupts: HDMI interrupt number

- ports: contain a port node with endpoint definitions as defined in

  Documentation/devicetree/bindings/media/video-interfaces.txt. For

  vopb,set the reg = <0> and set the reg = <1> for vopl.

- reg-io-width: the width of the reg:1,4, the value should be 4 on

  rk3288 platform



Optional properties

- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing

- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"



Example:

hdmi: hdmi@ff980000 {

	compatible = "rockchip,rk3288-dw-hdmi";

	reg = <0xff980000 0x20000>;

	reg-io-width = <4>;

	ddc-i2c-bus = <&i2c5>;

	rockchip,grf = <&grf>;

	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;

	clock-names = "iahb", "isfr";

	status = "disabled";

	ports {

		hdmi_in: port {

			#address-cells = <1>;

			#size-cells = <0>;

			hdmi_in_vopb: endpoint@0 {

				reg = <0>;

				remote-endpoint = <&vopb_out_hdmi>;

			};

			hdmi_in_vopl: endpoint@1 {

				reg = <1>;

				remote-endpoint = <&vopl_out_hdmi>;

			};

		};

	};

};

drivers/gpu/drm/bridge/Kconfig

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@@ -3,3 +3,8 @@ config DRM_PTN3460 
	depends on DRM

	select DRM_KMS_HELPER

	---help---



config DRM_DW_HDMI

	tristate

	depends on DRM

	select DRM_KMS_HELPER

drivers/gpu/drm/bridge/Makefile

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ccflags-y := -Iinclude/drm



obj-$(CONFIG_DRM_PTN3460) += ptn3460.o

obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o

drivers/gpu/drm/imx/imx-hdmi.c→drivers/gpu/drm/bridge/dw_hdmi.c

+336 −388

File changed and moved.

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