Loading arch/arm/boot/dts/qcom/sdxpoorwills-coresight.dtsi +0 −27 Original line number Diff line number Diff line Loading @@ -342,15 +342,6 @@ }; port@3 { reg = <2>; tpda_in_tpdm_dcc: endpoint { slave-mode; remote-endpoint = <&tpdm_dcc_out_tpda>; }; }; port@4 { reg = <5>; tpda_in_tpdm_center: endpoint { slave-mode; Loading Loading @@ -396,24 +387,6 @@ }; }; tpdm_dcc: tpdm@6870280 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b968>; reg = <0x6870280 0x1000>; reg-names = "tpdm-base"; coresight-name = "coresight-tpdm-dcc"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; port{ tpdm_dcc_out_tpda: endpoint { remote-endpoint = <&tpda_in_tpdm_dcc>; }; }; }; tpdm_vsense: tpdm@6840000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b968>; Loading Loading
arch/arm/boot/dts/qcom/sdxpoorwills-coresight.dtsi +0 −27 Original line number Diff line number Diff line Loading @@ -342,15 +342,6 @@ }; port@3 { reg = <2>; tpda_in_tpdm_dcc: endpoint { slave-mode; remote-endpoint = <&tpdm_dcc_out_tpda>; }; }; port@4 { reg = <5>; tpda_in_tpdm_center: endpoint { slave-mode; Loading Loading @@ -396,24 +387,6 @@ }; }; tpdm_dcc: tpdm@6870280 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b968>; reg = <0x6870280 0x1000>; reg-names = "tpdm-base"; coresight-name = "coresight-tpdm-dcc"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; port{ tpdm_dcc_out_tpda: endpoint { remote-endpoint = <&tpda_in_tpdm_dcc>; }; }; }; tpdm_vsense: tpdm@6840000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b968>; Loading