drm/radeon: rework vm_flush parameters (faffaf62) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/radeon/cik.c

+10 −13

Original line number	Original line	Diff line number	Diff line
	@@ -5982,26 +5982,23 @@ static void cik_vm_decode_fault(struct radeon_device *rdev,
	* Update the page table base and flush the VM TLB		* Update the page table base and flush the VM TLB
	* using the CP (CIK).		* using the CP (CIK).
	*/		*/
	void cik_vm_flush(struct radeon_device rdev, int ridx, struct radeon_vm vm)		void cik_vm_flush(struct radeon_device rdev, struct radeon_ring ring,
			unsigned vm_id, uint64_t pd_addr)
	{		{
	struct radeon_ring *ring = &rdev->ring[ridx];		int usepfp = (ring->idx == RADEON_RING_TYPE_GFX_INDEX);
	int usepfp = (ridx == RADEON_RING_TYPE_GFX_INDEX);

	if (vm == NULL)
	return;

	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));		radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) \|		radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) \|
	WRITE_DATA_DST_SEL(0)));		WRITE_DATA_DST_SEL(0)));
	if (vm->id < 8) {		if (vm_id < 8) {
	radeon_ring_write(ring,		radeon_ring_write(ring,
	(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);		(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
	} else {		} else {
	radeon_ring_write(ring,		radeon_ring_write(ring,
	(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);		(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
	}		}
	radeon_ring_write(ring, 0);		radeon_ring_write(ring, 0);
	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);		radeon_ring_write(ring, pd_addr >> 12);

	/* update SH_MEM_* regs */		/* update SH_MEM_* regs */
	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));		radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
	@@ -6009,7 +6006,7 @@ void cik_vm_flush(struct radeon_device rdev, int ridx, struct radeon_vm vm)
	WRITE_DATA_DST_SEL(0)));		WRITE_DATA_DST_SEL(0)));
	radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);		radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
	radeon_ring_write(ring, 0);		radeon_ring_write(ring, 0);
	radeon_ring_write(ring, VMID(vm->id));		radeon_ring_write(ring, VMID(vm_id));

	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));		radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) \|		radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) \|
	@@ -6030,7 +6027,7 @@ void cik_vm_flush(struct radeon_device rdev, int ridx, struct radeon_vm vm)
	radeon_ring_write(ring, VMID(0));		radeon_ring_write(ring, VMID(0));

	/* HDP flush */		/* HDP flush */
	cik_hdp_flush_cp_ring_emit(rdev, ridx);		cik_hdp_flush_cp_ring_emit(rdev, ring->idx);

	/* bits 0-15 are the VM contexts0-15 */		/* bits 0-15 are the VM contexts0-15 */
	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));		radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
	@@ -6038,7 +6035,7 @@ void cik_vm_flush(struct radeon_device rdev, int ridx, struct radeon_vm vm)
	WRITE_DATA_DST_SEL(0)));		WRITE_DATA_DST_SEL(0)));
	radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);		radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
	radeon_ring_write(ring, 0);		radeon_ring_write(ring, 0);
	radeon_ring_write(ring, 1 << vm->id);		radeon_ring_write(ring, 1 << vm_id);

	/* compute doesn't have PFP */		/* compute doesn't have PFP */
	if (usepfp) {		if (usepfp) {

drivers/gpu/drm/radeon/cik_sdma.c

+9 −13

Original line number	Original line	Diff line number	Diff line
	@@ -901,25 +901,21 @@ void cik_sdma_vm_pad_ib(struct radeon_ib *ib)
	* Update the page table base and flush the VM TLB		* Update the page table base and flush the VM TLB
	* using sDMA (CIK).		* using sDMA (CIK).
	*/		*/
	void cik_dma_vm_flush(struct radeon_device rdev, int ridx, struct radeon_vm vm)		void cik_dma_vm_flush(struct radeon_device rdev, struct radeon_ring ring,
			unsigned vm_id, uint64_t pd_addr)
	{		{
	struct radeon_ring *ring = &rdev->ring[ridx];

	if (vm == NULL)
	return;

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));		radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
	if (vm->id < 8) {		if (vm_id < 8) {
	radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);		radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
	} else {		} else {
	radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);		radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
	}		}
	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);		radeon_ring_write(ring, pd_addr >> 12);

	/* update SH_MEM_* regs */		/* update SH_MEM_* regs */
	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));		radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
	radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);		radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
	radeon_ring_write(ring, VMID(vm->id));		radeon_ring_write(ring, VMID(vm_id));

	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));		radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
	radeon_ring_write(ring, SH_MEM_BASES >> 2);		radeon_ring_write(ring, SH_MEM_BASES >> 2);
	@@ -942,11 +938,11 @@ void cik_dma_vm_flush(struct radeon_device rdev, int ridx, struct radeon_vm vm
	radeon_ring_write(ring, VMID(0));		radeon_ring_write(ring, VMID(0));

	/* flush HDP */		/* flush HDP */
	cik_sdma_hdp_flush_ring_emit(rdev, ridx);		cik_sdma_hdp_flush_ring_emit(rdev, ring->idx);

	/* flush TLB */		/* flush TLB */
	radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));		radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
	radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);		radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
	radeon_ring_write(ring, 1 << vm->id);		radeon_ring_write(ring, 1 << vm_id);
	}		}

drivers/gpu/drm/radeon/ni.c

+5 −9

Original line number	Original line	Diff line number	Diff line
	@@ -2502,15 +2502,11 @@ void cayman_vm_decode_fault(struct radeon_device *rdev,
	* Update the page table base and flush the VM TLB		* Update the page table base and flush the VM TLB
	* using the CP (cayman-si).		* using the CP (cayman-si).
	*/		*/
	void cayman_vm_flush(struct radeon_device rdev, int ridx, struct radeon_vm vm)		void cayman_vm_flush(struct radeon_device rdev, struct radeon_ring ring,
			unsigned vm_id, uint64_t pd_addr)
	{		{
	struct radeon_ring *ring = &rdev->ring[ridx];		radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0));
			radeon_ring_write(ring, pd_addr >> 12);
	if (vm == NULL)
	return;

	radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);

	/* flush hdp cache */		/* flush hdp cache */
	radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));		radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
	@@ -2518,7 +2514,7 @@ void cayman_vm_flush(struct radeon_device rdev, int ridx, struct radeon_vm vm)

	/* bits 0-7 are the VM contexts0-7 */		/* bits 0-7 are the VM contexts0-7 */
	radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));		radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
	radeon_ring_write(ring, 1 << vm->id);		radeon_ring_write(ring, 1 << vm_id);

	/* sync PFP to ME, otherwise we might get invalid PFP reads */		/* sync PFP to ME, otherwise we might get invalid PFP reads */
	radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));		radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

drivers/gpu/drm/radeon/ni_dma.c

+5 −9

Original line number	Original line	Diff line number	Diff line
	@@ -446,16 +446,12 @@ void cayman_dma_vm_pad_ib(struct radeon_ib *ib)
	ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);		ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
	}		}

	void cayman_dma_vm_flush(struct radeon_device rdev, int ridx, struct radeon_vm vm)		void cayman_dma_vm_flush(struct radeon_device rdev, struct radeon_ring ring,
			unsigned vm_id, uint64_t pd_addr)
	{		{
	struct radeon_ring *ring = &rdev->ring[ridx];

	if (vm == NULL)
	return;

	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
	radeon_ring_write(ring, (0xf << 16) \| ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));		radeon_ring_write(ring, (0xf << 16) \| ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2));
	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);		radeon_ring_write(ring, pd_addr >> 12);

	/* flush hdp cache */		/* flush hdp cache */
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
	@@ -465,6 +461,6 @@ void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm
	/* bits 0-7 are the VM contexts0-7 */		/* bits 0-7 are the VM contexts0-7 */
	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
	radeon_ring_write(ring, (0xf << 16) \| (VM_INVALIDATE_REQUEST >> 2));		radeon_ring_write(ring, (0xf << 16) \| (VM_INVALIDATE_REQUEST >> 2));
	radeon_ring_write(ring, 1 << vm->id);		radeon_ring_write(ring, 1 << vm_id);
	}		}

drivers/gpu/drm/radeon/radeon.h

+3 −2

Original line number	Original line	Diff line number	Diff line
	@@ -1798,7 +1798,8 @@ struct radeon_asic_ring {
	void (hdp_flush)(struct radeon_device rdev, struct radeon_ring *ring);		void (hdp_flush)(struct radeon_device rdev, struct radeon_ring *ring);
	bool (emit_semaphore)(struct radeon_device rdev, struct radeon_ring *cp,		bool (emit_semaphore)(struct radeon_device rdev, struct radeon_ring *cp,
	struct radeon_semaphore *semaphore, bool emit_wait);		struct radeon_semaphore *semaphore, bool emit_wait);
	void (vm_flush)(struct radeon_device rdev, int ridx, struct radeon_vm *vm);		void (vm_flush)(struct radeon_device rdev, struct radeon_ring *ring,
			unsigned vm_id, uint64_t pd_addr);

	/* testing functions */		/* testing functions */
	int (ring_test)(struct radeon_device rdev, struct radeon_ring *cp);		int (ring_test)(struct radeon_device rdev, struct radeon_ring *cp);
	@@ -2850,7 +2851,7 @@ static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
	#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))		#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
	#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))		#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
	#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))		#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
	#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))		#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
	#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))		#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
	#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))		#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
	#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))		#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))