Merge "usb: phy: Add snapshot of USB PHY drivers" into msm-4.8

MSM USB PHY transceivers

SSUSB-QMP PHY

Required properties:

 - compatible: Should be "qcom,usb-ssphy-qmp", "qcom,usb-ssphy-qmp-v1" or

   "qcom,usb-ssphy-qmp-v2"

 - reg: Address and length of the register set for the device

   Required regs are:

   "qmp_phy_base" : QMP PHY Base register set.

 - "vls_clamp_reg" : top-level CSR register to be written to enable phy vls

   clamp which allows phy to detect autonomous mode.

 - <supply-name>-supply: phandle to the regulator device tree node

   Required "supply-name" examples are:

	"vdd" : vdd supply for SSPHY digital circuit operation

	"core" : high-voltage analog supply for SSPHY

 - clocks: a list of phandles to the PHY clocks. Use as per

   Documentation/devicetree/bindings/clock/clock-bindings.txt

 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

   property. Required clocks are "aux_clk" and "pipe_clk".

 - qcom,vdd-voltage-level: This property must be a list of three integer

   values (no, min, max) where each value represents either a voltage in

   microvolts or a value corresponding to voltage corner

 - qcom,qmp-phy-init-seq: QMP PHY initialization sequence with reg offset, its

   value, delay after register write. It is not must property to have for emulation.

 - qcom,qmp-phy-reg-offset: Provides important phy register offsets in an order

   defined in the phy driver. Provide below mentioned register offsets in order:

   USB3_PHY_PCS_STATUS,

   USB3_PHY_AUTONOMOUS_MODE_CTRL,

   USB3_PHY_LFPS_RXTERM_IRQ_CLEAR,

   USB3_PHY_POWER_DOWN_CONTROL,

   USB3_PHY_SW_RESET,

   USB3_PHY_START

Optional properties:

 - reg: Additional register set of address and length to control QMP PHY are:

   "tcsr_usb3_dp_phymode" : top-level CSR register to be written to select

   super speed usb qmp phy.

 - clocks: a list of phandles to the PHY clocks. Use as per

   Documentation/devicetree/bindings/clock/clock-bindings.txt

 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

   property. Required clocks are "cfg_ahb_clk", "phy_reset" and "phy_phy_reset".

 - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to

   the USB PHY and the controller must rely on external VBUS notification in

   order to manually relay the notification to the SSPHY.

 - qcom,emulation: Indicates that we are running on emulation platform.

 - qcom,core-voltage-level: This property must be a list of three integer

   values (no, min, max) where each value represents either a voltage in

   microvolts or a value corresponding to voltage corner.

Example:

	ssphy0: ssphy@f9b38000 {

		compatible = "qcom,usb-ssphy-qmp";

		reg = <0xf9b38000 0x16c>,

			<0x01947244 0x4>;

		reg-names = "qmp_phy_base",

			"vls_clamp_reg";

		vdd-supply = <&pmd9635_l4>;

		vdda18-supply = <&pmd9635_l8>;

		qcom,vdd-voltage-level = <0 900000 1050000>;

		qcom,vbus-valid-override;

		clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,

			 <&clock_gcc clk_gcc_usb3_phy_pipe_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,

			 <&clock_gcc clk_gcc_usb3_phy_reset>,

			 <&clock_gcc clk_gcc_usb3phy_phy_reset>,

			 <&clock_gcc clk_ln_bb_clk1>,

			 <&clock_gcc clk_gcc_usb3_clkref_clk>;

		clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset",

			      "phy_phy_reset", "ref_clk_src", "ref_clk";

	};

QUSB2 High-Speed PHY

Required properties:

 - compatible: Should be "qcom,qusb2phy" or "qcom,qusb2phy-v2"

 - reg: Address and length of the QUSB2 PHY register set

 - reg-names: Should be "qusb_phy_base".

 - <supply-name>-supply: phandle to the regulator device tree node

   Required supplies are:

	"vdd" : vdd supply for digital circuit operation

	"vdda18" : 1.8v high-voltage analog supply

	"vdda33" : 3.3v high-voltage analog supply

 - qcom,vdd-voltage-level: This property must be a list of three integer

   values (no, min, max) where each value represents either a voltage in

   microvolts or a value corresponding to voltage corner

 - clocks: a list of phandles to the PHY clocks. Use as per

   Documentation/devicetree/bindings/clock/clock-bindings.txt

 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

   property. Required clock is "phy_reset".

 - phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode.

Optional properties:

 - reg-names: Additional registers corresponding with the following:

   "tune2_efuse_addr": EFUSE based register address to read TUNE2 parameter.

   via the QSCRATCH interface.

   "emu_phy_base" : phy base address used for programming emulation target phy.

   "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset.

 - clocks: a list of phandles to the PHY clocks. Use as per

   Documentation/devicetree/bindings/clock/clock-bindings.txt

 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"

   property. "cfg_ahb_clk", "ref_clk_src" and "ref_clk" are optional clocks.

 - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair.

 - qcom,qusb-phy-host-init-seq: QUSB PHY initialization sequence for host mode

   with value,reg pair.

 - qcom,emu-init-seq : emulation initialization sequence with value,reg pair.

 - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair.

 - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair.

 - qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register

 - qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble

 - qcom,emulation: Indicates that we are running on emulation platform.

 - qcom,hold-reset: Indicates that hold QUSB PHY into reset state.

 - qcom,phy-clk-scheme: Should be one of "cml" or "cmos" if ref_clk_addr is provided.

 - qcom,major-rev: provide major revision number to differentiate power up sequence. default is 2.0

Example:

	qusb_phy: qusb@f9b39000 {

		compatible = "qcom,qusb2phy";

		reg = <0x00079000 0x7000>;

		reg-names = "qusb_phy_base";

		vdd-supply = <&pm8994_s2_corner>;

		vdda18-supply = <&pm8994_l6>;

		vdda33-supply = <&pm8994_l24>;

		qcom,vdd-voltage-level = <1 5 7>;

		qcom,tune2-efuse-bit-pos = <21>;

		qcom,tune2-efuse-num-bits = <3>;

		clocks = <&clock_rpm clk_ln_bb_clk>,

			 <&clock_gcc clk_gcc_rx2_usb1_clkref_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,

			 <&clock_gcc clk_gcc_qusb2_phy_reset>;

		clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", "phy_reset";

	};

	  this interface to expose it capabilities to the userspace

	  and thereby allowing userspace to change the port mode.

config USB_MSM_SSPHY_QMP

	tristate "MSM SSUSB QMP PHY Driver"

	depends on ARCH_QCOM

	select USB_PHY

	help

	  Enable this to support the SuperSpeed USB transceiver on MSM chips.

	  This driver supports the PHY which uses the QSCRATCH-based register

	  set for its control sequences, normally paired with newer DWC3-based

	  SuperSpeed controllers.

config MSM_QUSB_PHY

	tristate "MSM QUSB2 PHY Driver"

	depends on ARCH_QCOM

	select USB_PHY

	help

	  Enable this to support the QUSB2 PHY on MSM chips. This driver supports

	  the high-speed PHY which is usually paired with either the ChipIdea or

	  Synopsys DWC3 USB IPs on MSM SOCs. This driver expects to configure the

	  PHY with a dedicated register I/O memory region.

endmenu

obj-$(CONFIG_USB_ULPI)			+= phy-ulpi.o

obj-$(CONFIG_USB_ULPI_VIEWPORT)		+= phy-ulpi-viewport.o

obj-$(CONFIG_KEYSTONE_USB_PHY)		+= phy-keystone.o

obj-$(CONFIG_USB_MSM_SSPHY_QMP)     	+= phy-msm-ssusb-qmp.o

obj-$(CONFIG_MSM_QUSB_PHY)              += phy-msm-qusb.o phy-msm-qusb-v2.o