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Commit fa8d1d6c authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'for_2.6.33rc_d' of git://git.pwsan.com/linux-2.6 into omap-fixes-for-linus

parents 7284ce6c af022faf

arch/arm/mach-omap1/clock.c

+3 −3
Original line number Diff line number Diff line
@@ -214,8 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) 
	struct mpu_rate * ptr;

	unsigned long dpll1_rate, ref_rate;



	dpll1_rate = clk_get_rate(ck_dpll1_p);

	ref_rate = clk_get_rate(ck_ref_p);

	dpll1_rate = ck_dpll1_p->rate;

	ref_rate = ck_ref_p->rate;



	for (ptr = omap1_rate_table; ptr->rate; ptr++) {

		if (ptr->xtal != ref_rate)
@@ -306,7 +306,7 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) 
	long highest_rate;

	unsigned long ref_rate;



	ref_rate = clk_get_rate(ck_ref_p);

	ref_rate = ck_ref_p->rate;



	highest_rate = -EINVAL;

arch/arm/mach-omap2/clock34xx_data.c

+0 −4
Original line number Diff line number Diff line
@@ -671,7 +671,6 @@ static struct clk dpll4_m3x2_ck = { 
	.name		= "dpll4_m3x2_ck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &dpll4_m3_ck,

	.init		= &omap2_init_clksel_parent,

	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),

	.enable_bit	= OMAP3430_PWRDN_TV_SHIFT,

	.flags		= INVERT_ENABLE,
@@ -811,7 +810,6 @@ static struct clk dpll4_m6x2_ck = { 
	.name		= "dpll4_m6x2_ck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &dpll4_m6_ck,

	.init		= &omap2_init_clksel_parent,

	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),

	.enable_bit	= OMAP3430_PWRDN_EMU_PERIPH_SHIFT,

	.flags		= INVERT_ENABLE,
@@ -1047,7 +1045,6 @@ static struct clk iva2_ck = { 
	.name		= "iva2_ck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &dpll2_m2_ck,

	.init		= &omap2_init_clksel_parent,

	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),

	.enable_bit	= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,

	.clkdm_name	= "iva2_clkdm",
@@ -1121,7 +1118,6 @@ static struct clk gfx_l3_ck = { 
	.name		= "gfx_l3_ck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &l3_ick,

	.init		= &omap2_init_clksel_parent,

	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),

	.enable_bit	= OMAP_EN_GFX_SHIFT,

	.recalc		= &followparent_recalc,

arch/arm/mach-omap2/clock44xx_data.c

+31 −31
Original line number Diff line number Diff line
@@ -346,37 +346,37 @@ static struct clk aess_fclk = { 
};



static const struct clksel_rate div31_1to31_rates[] = {

	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },

	{ .div = 2, .val = 1, .flags = RATE_IN_4430 },

	{ .div = 3, .val = 2, .flags = RATE_IN_4430 },

	{ .div = 4, .val = 3, .flags = RATE_IN_4430 },

	{ .div = 5, .val = 4, .flags = RATE_IN_4430 },

	{ .div = 6, .val = 5, .flags = RATE_IN_4430 },

	{ .div = 7, .val = 6, .flags = RATE_IN_4430 },

	{ .div = 8, .val = 7, .flags = RATE_IN_4430 },

	{ .div = 9, .val = 8, .flags = RATE_IN_4430 },

	{ .div = 10, .val = 9, .flags = RATE_IN_4430 },

	{ .div = 11, .val = 10, .flags = RATE_IN_4430 },

	{ .div = 12, .val = 11, .flags = RATE_IN_4430 },

	{ .div = 13, .val = 12, .flags = RATE_IN_4430 },

	{ .div = 14, .val = 13, .flags = RATE_IN_4430 },

	{ .div = 15, .val = 14, .flags = RATE_IN_4430 },

	{ .div = 16, .val = 15, .flags = RATE_IN_4430 },

	{ .div = 17, .val = 16, .flags = RATE_IN_4430 },

	{ .div = 18, .val = 17, .flags = RATE_IN_4430 },

	{ .div = 19, .val = 18, .flags = RATE_IN_4430 },

	{ .div = 20, .val = 19, .flags = RATE_IN_4430 },

	{ .div = 21, .val = 20, .flags = RATE_IN_4430 },

	{ .div = 22, .val = 21, .flags = RATE_IN_4430 },

	{ .div = 23, .val = 22, .flags = RATE_IN_4430 },

	{ .div = 24, .val = 23, .flags = RATE_IN_4430 },

	{ .div = 25, .val = 24, .flags = RATE_IN_4430 },

	{ .div = 26, .val = 25, .flags = RATE_IN_4430 },

	{ .div = 27, .val = 26, .flags = RATE_IN_4430 },

	{ .div = 28, .val = 27, .flags = RATE_IN_4430 },

	{ .div = 29, .val = 28, .flags = RATE_IN_4430 },

	{ .div = 30, .val = 29, .flags = RATE_IN_4430 },

	{ .div = 31, .val = 30, .flags = RATE_IN_4430 },

	{ .div = 1, .val = 1, .flags = RATE_IN_4430 },

	{ .div = 2, .val = 2, .flags = RATE_IN_4430 },

	{ .div = 3, .val = 3, .flags = RATE_IN_4430 },

	{ .div = 4, .val = 4, .flags = RATE_IN_4430 },

	{ .div = 5, .val = 5, .flags = RATE_IN_4430 },

	{ .div = 6, .val = 6, .flags = RATE_IN_4430 },

	{ .div = 7, .val = 7, .flags = RATE_IN_4430 },

	{ .div = 8, .val = 8, .flags = RATE_IN_4430 },

	{ .div = 9, .val = 9, .flags = RATE_IN_4430 },

	{ .div = 10, .val = 10, .flags = RATE_IN_4430 },

	{ .div = 11, .val = 11, .flags = RATE_IN_4430 },

	{ .div = 12, .val = 12, .flags = RATE_IN_4430 },

	{ .div = 13, .val = 13, .flags = RATE_IN_4430 },

	{ .div = 14, .val = 14, .flags = RATE_IN_4430 },

	{ .div = 15, .val = 15, .flags = RATE_IN_4430 },

	{ .div = 16, .val = 16, .flags = RATE_IN_4430 },

	{ .div = 17, .val = 17, .flags = RATE_IN_4430 },

	{ .div = 18, .val = 18, .flags = RATE_IN_4430 },

	{ .div = 19, .val = 19, .flags = RATE_IN_4430 },

	{ .div = 20, .val = 20, .flags = RATE_IN_4430 },

	{ .div = 21, .val = 21, .flags = RATE_IN_4430 },

	{ .div = 22, .val = 22, .flags = RATE_IN_4430 },

	{ .div = 23, .val = 23, .flags = RATE_IN_4430 },

	{ .div = 24, .val = 24, .flags = RATE_IN_4430 },

	{ .div = 25, .val = 25, .flags = RATE_IN_4430 },

	{ .div = 26, .val = 26, .flags = RATE_IN_4430 },

	{ .div = 27, .val = 27, .flags = RATE_IN_4430 },

	{ .div = 28, .val = 28, .flags = RATE_IN_4430 },

	{ .div = 29, .val = 29, .flags = RATE_IN_4430 },

	{ .div = 30, .val = 30, .flags = RATE_IN_4430 },

	{ .div = 31, .val = 31, .flags = RATE_IN_4430 },

	{ .div = 0 },

};

arch/arm/mach-omap2/omap_hwmod.c

+2 −1
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ static int _update_sysc_cache(struct omap_hwmod *oh) 


	oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);



	if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE))

		oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;



	return 0;

arch/arm/mach-omap2/prm.h

+2 −0
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ 
		OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))

#define OMAP44XX_PRM_REGADDR(module, reg)				\

		OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))

#define OMAP44XX_CHIRONSS_REGADDR(module, reg)				\

		OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))



#include "prm44xx.h"