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Commit fa555837 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: fixup the plane->pipe fixup code 

We need to check whether the _other plane is on our pipe, not whether
our plane is on the other pipe. Otherwise if not both pipes/planes are
active, we won't properly clean up the mess and set up our desired
plane->pipe mapping.

v2: Fixup the logic, I've totally fumbled it. Noticed by Chris Wilson.

v3: I've checked Bspec, and the flexible plane->pipe mapping is a
gen2/3 feature, so test for that instead of PCH_SPLIT

v4: Check whether we indeed have 2 pipes before checking the other
pipe, to avoid upsetting i845g/i865g. Noticed by Chris Wilson.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51265
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49838


Tested-by: default avatarDave Airlie <airlied@gmail.com>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk> #855gm
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ccd0d36e

drivers/gpu/drm/i915/intel_display.c

+23 −11
Original line number Diff line number Diff line
@@ -8058,29 +8058,42 @@ static void intel_enable_pipe_a(struct drm_device *dev) 


}



static bool

intel_check_plane_mapping(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;

	u32 reg, val;



	if (dev_priv->num_pipe == 1)

		return true;



	reg = DSPCNTR(!crtc->plane);

	val = I915_READ(reg);



	if ((val & DISPLAY_PLANE_ENABLE) &&

	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))

		return false;



	return true;

}



static void intel_sanitize_crtc(struct intel_crtc *crtc)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 reg, val;

	u32 reg;



	/* Clear any frame start delays used for debugging left by the BIOS */

	reg = PIPECONF(crtc->pipe);

	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);



	/* We need to sanitize the plane -> pipe mapping first because this will

	 * disable the crtc (and hence change the state) if it is wrong. */

	if (!HAS_PCH_SPLIT(dev)) {

	 * disable the crtc (and hence change the state) if it is wrong. Note

	 * that gen4+ has a fixed plane -> pipe mapping.  */

	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {

		struct intel_connector *connector;

		bool plane;



		reg = DSPCNTR(crtc->plane);

		val = I915_READ(reg);



		if ((val & DISPLAY_PLANE_ENABLE) == 0 &&

		    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))

			goto ok;



		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",

			      crtc->base.base.id);
@@ -8104,7 +8117,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) 
		WARN_ON(crtc->active);

		crtc->base.enabled = false;

	}

ok:



	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&

	    crtc->pipe == PIPE_A && !crtc->active) {