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Commit fa2a1ea2 authored by Sunil Paidimarri's avatar Sunil Paidimarri Committed by Gerrit - the friendly Code Review server
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msm: phy: Fix WOL disable for Micrel PHY 



For Micrel 9031 phy driver add functionality to
handle WOL disable using ethtool.

Change-Id: I3908a0caf3d81177862cc4ad626f4d5fb19d89ed
Acked-by: default avatarNisha Menon <nmenon@qti.qualcomm.com>
Signed-off-by: default avatarSunil Paidimarri <hisunil@codeaurora.org>
parent ef5e807a

drivers/net/phy/micrel.c

+46 −29
Original line number Diff line number Diff line
@@ -487,21 +487,21 @@ static int ksz9031_ack_interrupt(struct phy_device *phydev) 
	rc = phy_read(phydev, MII_KSZPHY_INTCS);



	reg_value = ksz9031_extended_read(

	   phydev, OP_DATA, 0x2, MII_KSZPHY_OMSO_REG);

	if (reg_value & MII_KSZPHY_OMSO_PME_N2) {

	   phydev, OP_DATA, 0x2, MII_KSZPHY_WOL_CTRL_REG);

	if (reg_value & MII_KSZPHY_WOL_CTRL_PME_N2) {

		/* PME output is cleared by disabling the PME trigger src */

		reg_value = ksz9031_extended_read(

		   phydev, OP_DATA, 0x2, MII_KSZPHY_WOL_CTRL_REG);

		reg_value &= ~MII_KSZPHY_WOL_MAGIC_PKT;

		reg_value &= ~MII_KSZPHY_WOL_LINK_UP;

		reg_value &= ~MII_KSZPHY_WOL_LINK_DOWN;

		reg_value &= ~(MII_KSZPHY_WOL_MAGIC_PKT |

					   MII_KSZPHY_WOL_LINK_UP |

					   MII_KSZPHY_WOL_LINK_DOWN);

		ksz9031_extended_write(

		   phydev, OP_DATA, 0x2, MII_KSZPHY_WOL_CTRL_REG, reg_value);

		reg_value = ksz9031_extended_read(

		   phydev, OP_DATA, 0x2, MII_KSZPHY_WOL_CTRL_REG);

		reg_value |= MII_KSZPHY_WOL_MAGIC_PKT;

		reg_value |= MII_KSZPHY_WOL_LINK_UP;

		reg_value |= MII_KSZPHY_WOL_LINK_DOWN;

		reg_value |= (MII_KSZPHY_WOL_MAGIC_PKT |

					  MII_KSZPHY_WOL_LINK_UP |

					  MII_KSZPHY_WOL_LINK_DOWN);

		ksz9031_extended_write(

		   phydev, OP_DATA, 0x2, MII_KSZPHY_WOL_CTRL_REG, reg_value);

	}
@@ -838,18 +838,35 @@ static int kszphy_probe(struct phy_device *phydev) 
	return 0;

}



static void ksz9031_set_wol_settings(struct phy_device *phydev)

static void ksz9031_set_wol_settings(

	struct phy_device *phydev, bool is_wol_enabled)

{

	u32 reg_value;

	u32 reg_value1;



	/* Enable both PHY and PME_N2 interrupts */

	reg_value = ksz9031_extended_read(

		   phydev, OP_DATA, 0x2, MII_KSZPHY_WOL_CTRL_REG);

	if (is_wol_enabled) {

		/* Enable both PHY and PME_N2 interrupts */

		reg_value |= MII_KSZPHY_WOL_CTRL_PME_N2;

		reg_value &= ~MII_KSZPHY_WOL_CTRL_INT_N;

	reg_value |= MII_KSZPHY_WOL_MAGIC_PKT;

	reg_value |= MII_KSZPHY_WOL_LINK_UP;

	reg_value |= MII_KSZPHY_WOL_LINK_DOWN;

		reg_value |= (MII_KSZPHY_WOL_MAGIC_PKT |

					  MII_KSZPHY_WOL_LINK_UP |

					  MII_KSZPHY_WOL_LINK_DOWN);

		/* Enable PME_N2 output */

		reg_value1 = ksz9031_extended_read(

		   phydev, OP_DATA, 0x2, MII_KSZPHY_OMSO_REG);

		reg_value1 |= MII_KSZPHY_OMSO_PME_N2;

		ksz9031_extended_write(

		   phydev, OP_DATA, 0x2, MII_KSZPHY_OMSO_REG, reg_value1);

	} else {

		/* Disable PME_N2 output and enable only PHY interrupt */

		reg_value &= ~MII_KSZPHY_WOL_CTRL_PME_N2;

		reg_value |= MII_KSZPHY_WOL_CTRL_INT_N;

		reg_value &= ~(MII_KSZPHY_WOL_MAGIC_PKT |

					   MII_KSZPHY_WOL_LINK_UP |

					   MII_KSZPHY_WOL_LINK_DOWN);

	}

	ksz9031_extended_write(

	   phydev, OP_DATA, 0x2, MII_KSZPHY_WOL_CTRL_REG, reg_value);

}
@@ -860,7 +877,7 @@ static int ksz9031_set_wol( 
	struct net_device *ndev = phydev->attached_dev;

	const u8 *mac;

	int ret = 0;

	u32 reg_value;

	bool is_wol_enabled = false;



	if (!ndev)

		return -ENODEV;
@@ -879,15 +896,9 @@ static int ksz9031_set_wol( 
		   phydev, OP_DATA, 0x2, 0x13, mac[1] | (mac[0] << 8));



		/* Enable WOL interrupt for magic pkt, link up and down */

		ksz9031_set_wol_settings(phydev);



		/* Enable PME_N2 output */

		reg_value = ksz9031_extended_read(

		   phydev, OP_DATA, 0x2, MII_KSZPHY_OMSO_REG);

		reg_value |= MII_KSZPHY_OMSO_PME_N2;

		ksz9031_extended_write(

		   phydev, OP_DATA, 0x2, MII_KSZPHY_OMSO_REG, reg_value);

		is_wol_enabled = true;

	}

	ksz9031_set_wol_settings(phydev, is_wol_enabled);



	return ret;

}
@@ -901,8 +912,8 @@ static void ksz9031_get_wol( 
	wol->wolopts = 0;



	reg_value = ksz9031_extended_read(

	   phydev, OP_DATA, 0x2, MII_KSZPHY_OMSO_REG);

	if (reg_value & MII_KSZPHY_OMSO_PME_N2)

	   phydev, OP_DATA, 0x2, MII_KSZPHY_WOL_CTRL_REG);

	if (reg_value & MII_KSZPHY_WOL_CTRL_PME_N2)

		wol->wolopts |= WAKE_MAGIC;

}
@@ -915,8 +926,8 @@ static int ksz9031_suspend(struct phy_device *phydev) 
	mutex_lock(&phydev->lock);



	reg_value = ksz9031_extended_read(

	   phydev, OP_DATA, 0x2, MII_KSZPHY_OMSO_REG);

	wol_enabled = reg_value & MII_KSZPHY_OMSO_PME_N2;

	   phydev, OP_DATA, 0x2, MII_KSZPHY_WOL_CTRL_REG);

	wol_enabled = reg_value & MII_KSZPHY_WOL_CTRL_PME_N2;



	value = phy_read(phydev, MII_BMCR);

	if (wol_enabled)
@@ -942,6 +953,12 @@ static int ksz9031_resume(struct phy_device *phydev) 


	mutex_unlock(&phydev->lock);



	if (phy_interrupt_is_valid(phydev) || phydev->interrupts ==

		PHY_INTERRUPT_ENABLED) {

		if (phydev->drv->config_intr)

			phydev->drv->config_intr(phydev);

	}



	return 0;

}