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Commit fa0cf2f2 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/radeon: rework VCE FW size calculation 



Previously we were completely over allocating, fix this
by actually implementing the size calculation.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 72b9076b

drivers/gpu/drm/radeon/radeon.h

+0 −2
Original line number Diff line number Diff line
@@ -1709,8 +1709,6 @@ int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 
 * VCE

 */

#define RADEON_MAX_VCE_HANDLES	16

#define RADEON_VCE_STACK_SIZE	(1024*1024)

#define RADEON_VCE_HEAP_SIZE	(4*1024*1024)



struct radeon_vce {

	struct radeon_bo	*vcpu_bo;

drivers/gpu/drm/radeon/radeon_asic.h

+1 −0
Original line number Diff line number Diff line
@@ -974,6 +974,7 @@ int vce_v1_0_init(struct radeon_device *rdev); 
int vce_v1_0_start(struct radeon_device *rdev);



/* vce v2.0 */

unsigned vce_v2_0_bo_size(struct radeon_device *rdev);

int vce_v2_0_resume(struct radeon_device *rdev);



#endif

drivers/gpu/drm/radeon/radeon_vce.c

+1 −2
Original line number Diff line number Diff line
@@ -123,8 +123,7 @@ int radeon_vce_init(struct radeon_device *rdev) 


	/* allocate firmware, stack and heap BO */



	size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) +

	       RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE;

	size = vce_v2_0_bo_size(rdev);

	r = radeon_bo_create(rdev, size, PAGE_SIZE, true,

			     RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL,

			     &rdev->vce.vcpu_bo);

drivers/gpu/drm/radeon/vce_v2_0.c

+13 −3
Original line number Diff line number Diff line
@@ -31,6 +31,10 @@ 
#include "radeon_asic.h"

#include "cikd.h"



#define VCE_V2_0_FW_SIZE	(256 * 1024)

#define VCE_V2_0_STACK_SIZE	(64 * 1024)

#define VCE_V2_0_DATA_SIZE	(23552 * RADEON_MAX_VCE_HANDLES)



static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)

{

	u32 tmp;
@@ -140,6 +144,12 @@ static void vce_v2_0_init_cg(struct radeon_device *rdev) 
	WREG32(VCE_CLOCK_GATING_B, tmp);

}



unsigned vce_v2_0_bo_size(struct radeon_device *rdev)

{

	WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE);

	return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE;

}



int vce_v2_0_resume(struct radeon_device *rdev)

{

	uint64_t addr = rdev->vce.gpu_addr;
@@ -159,17 +169,17 @@ int vce_v2_0_resume(struct radeon_device *rdev) 
	WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);



	addr &= 0xff;

	size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);

	size = VCE_V2_0_FW_SIZE;

	WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);

	WREG32(VCE_VCPU_CACHE_SIZE0, size);



	addr += size;

	size = RADEON_VCE_STACK_SIZE;

	size = VCE_V2_0_STACK_SIZE;

	WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);

	WREG32(VCE_VCPU_CACHE_SIZE1, size);



	addr += size;

	size = RADEON_VCE_HEAP_SIZE;

	size = VCE_V2_0_DATA_SIZE;

	WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);

	WREG32(VCE_VCPU_CACHE_SIZE2, size);