Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-2.6 (f966a13f) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/net/wireless/ath/ath5k/base.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -2294,6 +2294,8 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
		int i;
		bool needreset = false;

		mutex_lock(&sc->lock);

		for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
		if (sc->txqs[i].setup) {
		txq = &sc->txqs[i];
		@@ -2321,6 +2323,8 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
		ath5k_reset(sc, NULL, true);
		}

		mutex_unlock(&sc->lock);

		ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
		msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
		}

+5 −5

Original line number	Diff line number	Diff line
		@@ -679,10 +679,6 @@ static bool ar9002_hw_calibrate(struct ath_hw *ah,

		/* Do NF cal only at longer intervals */
		if (longcal \|\| nfcal_pending) {
		/* Do periodic PAOffset Cal */
		ar9002_hw_pa_cal(ah, false);
		ar9002_hw_olc_temp_compensation(ah);

		/*
		* Get the value from the previous NF cal and update
		* history buffer.
		@@ -697,8 +693,12 @@ static bool ar9002_hw_calibrate(struct ath_hw *ah,
		ath9k_hw_loadnf(ah, ah->curchan);
		}

		if (longcal)
		if (longcal) {
		ath9k_hw_start_nfcal(ah, false);
		/* Do periodic PAOffset Cal */
		ar9002_hw_pa_cal(ah, false);
		ar9002_hw_olc_temp_compensation(ah);
		}
		}

		return iscaldone;

+1 −1

Original line number	Diff line number	Diff line
		@@ -1842,7 +1842,7 @@ static const u32 ar9300_2p2_soc_preamble[][2] = {

		static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2] = {
		/* Addr allmodes */
		{0x00004040, 0x08212e5e},
		{0x00004040, 0x0821265e},
		{0x00004040, 0x0008003b},
		{0x00004044, 0x00000000},
		};

+2 −2

Original line number	Diff line number	Diff line
		@@ -146,8 +146,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
		/* Sleep Setting */

		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
		ar9300PciePhy_clkreq_enable_L1_2p2,
		ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
		ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
		ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
		2);

		/* Fast clock modal settings */

+1 −1