Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f94ddd78 authored by Kiran Gunda's avatar Kiran Gunda Committed by Subbaraman Narayanamurthy
Browse files

regulator: qpnp-oledb: Clear SPARE_CTL register during disable 



OLEDB_SPARE_CTL register bit is set by the PBS during the display enable
and is used during the display suspend to trigger the PBS event.
Hence, move clearing of the OLEDB_SPARE_CTL register to regulator disable.
Also enable the force_pd_ctl only for DRAX-A revisions <=2.0.

Change-Id: I339cefc91f94f772bc4f84e85f2471e1a73e4aed
Signed-off-by: default avatarKiran Gunda <kgunda@codeaurora.org>
parent 1b18856f

Documentation/devicetree/bindings/regulator/qpnp-oledb-regulator.txt

+0 −7
Original line number Diff line number Diff line
@@ -62,13 +62,6 @@ Required Node Structure 
		     rail.  This property is applicable only if qcom,ext-pin-ctl

		     property is specified and it is specific to PM660A.



- qcom,force-pd-control

	Usage:      optional

	Value type: <bool>

	Definition:  Used to enable the pull down control forcibly via SPMI by

		     disabling the pull down configuration done by hardware

		     automatically through SWIRE pulses.



- qcom,pbs-client

	Usage:      optional

	Value type: <phandle>

drivers/regulator/qpnp-oledb-regulator.c

+18 −12
Original line number Diff line number Diff line
@@ -377,12 +377,19 @@ static int qpnp_oledb_regulator_disable(struct regulator_dev *rdev) 
		}



		if (val & OLEDB_FORCE_PD_CTL_SPARE_BIT) {

			rc = qpnp_pbs_trigger_event(oledb->pbs_dev_node,

							trigger_bitmap);

			rc = qpnp_oledb_sec_masked_write(oledb, oledb->base +

					OLEDB_SPARE_CTL,

					OLEDB_FORCE_PD_CTL_SPARE_BIT, 0);

			if (rc < 0) {

				pr_err("Failed to trigger the PBS sequence\n");

				pr_err("Failed to write SPARE_CTL rc=%d\n", rc);

				return rc;

			}



			rc = qpnp_pbs_trigger_event(oledb->pbs_dev_node,

							trigger_bitmap);

			if (rc < 0)

				pr_err("Failed to trigger the PBS sequence\n");



			pr_debug("PBS event triggered\n");

		} else {

			pr_debug("OLEDB_SPARE_CTL register bit not set\n");
@@ -1123,8 +1130,14 @@ static int qpnp_oledb_parse_dt(struct qpnp_oledb *oledb) 
	oledb->pbs_control =

			of_property_read_bool(of_node, "qcom,pbs-control");



	oledb->force_pd_control =

			of_property_read_bool(of_node, "qcom,force-pd-control");

	/* Use the force_pd_control only for PM660A versions <= v2.0 */

	if (oledb->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE &&

				oledb->pmic_rev_id->rev4 <= PM660L_V2P0_REV4) {

		if (!(oledb->pmic_rev_id->rev4 == PM660L_V2P0_REV4 &&

			oledb->pmic_rev_id->rev2 > PM660L_V2P0_REV2)) {

			oledb->force_pd_control = true;

		}

	}



	if (oledb->force_pd_control) {

		oledb->pbs_dev_node = of_parse_phandle(of_node,
@@ -1222,13 +1235,6 @@ static int qpnp_oledb_force_pulldown_config(struct qpnp_oledb *oledb) 
	int rc = 0;

	u8 val;



	rc = qpnp_oledb_sec_masked_write(oledb, oledb->base +

		    OLEDB_SPARE_CTL, OLEDB_FORCE_PD_CTL_SPARE_BIT, 0);

	if (rc < 0) {

		pr_err("Failed to write SPARE_CTL rc=%d\n", rc);

		return rc;

	}



	val = 1;

	rc = qpnp_oledb_write(oledb, oledb->base + OLEDB_PD_CTL,

							&val, 1);

include/linux/qpnp/qpnp-revid.h

+5 −0
Original line number Diff line number Diff line
@@ -214,6 +214,11 @@ 
#define PM660L_V1P1_REV3	0x01

#define PM660L_V1P1_REV4	0x01



#define PM660L_V2P0_REV1	0x00

#define PM660L_V2P0_REV2	0x00

#define PM660L_V2P0_REV3	0x00

#define PM660L_V2P0_REV4	0x02



/* PMI8998 FAB_ID */

#define PMI8998_FAB_ID_SMIC	0x11

#define PMI8998_FAB_ID_GF	0x30