Merge "ARM: dts: msm: disable dynamic FPS feature for SDM845" (f80b13d0) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi

+0 −10

Original line number	Diff line number	Diff line
		@@ -510,11 +510,6 @@
		&dsi_dual_nt35597_truly_video {
		qcom,mdss-dsi-t-clk-post = <0x0D>;
		qcom,mdss-dsi-t-clk-pre = <0x2D>;
		qcom,mdss-dsi-min-refresh-rate = <53>;
		qcom,mdss-dsi-max-refresh-rate = <60>;
		qcom,mdss-dsi-pan-enable-dynamic-fps;
		qcom,mdss-dsi-pan-fps-update =
		"dfps_immediate_porch_mode_vfp";
		qcom,esd-check-enabled;
		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
		qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
		@@ -580,11 +575,6 @@
		&dsi_nt35597_truly_dsc_video {
		qcom,mdss-dsi-t-clk-post = <0x0b>;
		qcom,mdss-dsi-t-clk-pre = <0x23>;
		qcom,mdss-dsi-min-refresh-rate = <53>;
		qcom,mdss-dsi-max-refresh-rate = <60>;
		qcom,mdss-dsi-pan-enable-dynamic-fps;
		qcom,mdss-dsi-pan-fps-update =
		"dfps_immediate_porch_mode_vfp";
		qcom,esd-check-enabled;
		qcom,mdss-dsi-panel-status-check-mode = "reg_read";
		qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];

drivers/gpu/drm/msm/msm_mmu.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -46,6 +46,12 @@ struct msm_mmu_funcs {
		struct dma_buf *dma_buf, int dir);
		void (destroy)(struct msm_mmu mmu);
		bool (is_domain_secure)(struct msm_mmu mmu);
		int (set_attribute)(struct msm_mmu mmu,
		enum iommu_attr attr, void *data);
		int (one_to_one_map)(struct msm_mmu mmu, uint32_t iova,
		uint32_t dest_address, uint32_t size, int prot);
		int (one_to_one_unmap)(struct msm_mmu mmu, uint32_t dest_address,
		uint32_t size);
		};

		struct msm_mmu {

drivers/gpu/drm/msm/msm_smmu.c

+71 −0

Original line number	Diff line number	Diff line
		@@ -113,6 +113,74 @@ static void msm_smmu_detach(struct msm_mmu mmu, const char const *names,
		dev_dbg(client->dev, "iommu domain detached\n");
		}

		static int msm_smmu_set_attribute(struct msm_mmu *mmu,
		enum iommu_attr attr, void *data)
		{
		struct msm_smmu *smmu = to_msm_smmu(mmu);
		struct msm_smmu_client *client = msm_smmu_to_client(smmu);
		struct iommu_domain *domain;
		int ret = 0;

		if (!client \|\| !client->mmu_mapping)
		return -ENODEV;

		domain = client->mmu_mapping->domain;
		if (!domain) {
		DRM_ERROR("Invalid domain ret:%d\n", ret);
		return -EINVAL;
		}

		ret = iommu_domain_set_attr(domain, attr, data);
		if (ret)
		DRM_ERROR("set domain attribute failed:%d\n", ret);

		return ret;
		}

		static int msm_smmu_one_to_one_unmap(struct msm_mmu *mmu,
		uint32_t dest_address, uint32_t size)
		{
		struct msm_smmu *smmu = to_msm_smmu(mmu);
		struct msm_smmu_client *client = msm_smmu_to_client(smmu);
		struct iommu_domain *domain;
		int ret = 0;

		if (!client \|\| !client->mmu_mapping)
		return -ENODEV;

		domain = client->mmu_mapping->domain;
		if (!domain)
		return -EINVAL;

		ret = iommu_unmap(domain, dest_address, size);
		if (ret != size)
		pr_err("smmu unmap failed\n");

		return 0;
		}

		static int msm_smmu_one_to_one_map(struct msm_mmu *mmu, uint32_t iova,
		uint32_t dest_address, uint32_t size, int prot)
		{
		struct msm_smmu *smmu = to_msm_smmu(mmu);
		struct msm_smmu_client *client = msm_smmu_to_client(smmu);
		struct iommu_domain *domain;
		int ret = 0;

		if (!client \|\| !client->mmu_mapping)
		return -ENODEV;

		domain = client->mmu_mapping->domain;
		if (!domain)
		return -EINVAL;

		ret = iommu_map(domain, dest_address, dest_address, size, prot);
		if (ret)
		pr_err("smmu map failed\n");

		return ret;
		}

		static int msm_smmu_map(struct msm_mmu *mmu, uint32_t iova,
		struct sg_table *sgt, int prot)
		{
		@@ -299,6 +367,9 @@ static const struct msm_mmu_funcs funcs = {
		.unmap_dma_buf = msm_smmu_unmap_dma_buf,
		.destroy = msm_smmu_destroy,
		.is_domain_secure = msm_smmu_is_domain_secure,
		.set_attribute = msm_smmu_set_attribute,
		.one_to_one_map = msm_smmu_one_to_one_map,
		.one_to_one_unmap = msm_smmu_one_to_one_unmap,
		};

		static struct msm_smmu_domain msm_smmu_domains[MSM_SMMU_DOMAIN_MAX] = {

drivers/gpu/drm/msm/sde/sde_encoder.c

+10 −4

Original line number	Diff line number	Diff line
		@@ -3453,16 +3453,21 @@ int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
		{
		struct sde_encoder_virt *sde_enc;
		struct sde_encoder_phys *phys;
		struct sde_kms *sde_kms = NULL;
		struct msm_drm_private *priv = NULL;
		bool needs_hw_reset = false;
		uint32_t ln_cnt1, ln_cnt2;
		unsigned int i;
		int rc, ret = 0;

		if (!drm_enc \|\| !params) {
		if (!drm_enc \|\| !params \|\| !drm_enc->dev \|\|
		!drm_enc->dev->dev_private) {
		SDE_ERROR("invalid args\n");
		return -EINVAL;
		}
		sde_enc = to_sde_encoder_virt(drm_enc);
		priv = drm_enc->dev->dev_private;
		sde_kms = to_sde_kms(priv->kms);

		SDE_DEBUG_ENC(sde_enc, "\n");
		SDE_EVT32(DRMID(drm_enc));
		@@ -3531,7 +3536,8 @@ int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
		}
		}

		if (_sde_encoder_is_dsc_enabled(drm_enc)) {
		if (_sde_encoder_is_dsc_enabled(drm_enc) &&
		!sde_kms->splash_data.cont_splash_en) {
		rc = _sde_encoder_dsc_setup(sde_enc, params);
		if (rc) {
		SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
		@@ -4398,8 +4404,8 @@ int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder)
		return ret;
		}

		if (conn->encoder) {
		conn->state->best_encoder = conn->encoder;
		if (sde_conn->encoder) {
		conn->state->best_encoder = sde_conn->encoder;
		SDE_DEBUG_ENC(sde_enc,
		"configured cstate->best_encoder to ID = %d\n",
		conn->state->best_encoder->base.id);

drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -891,6 +891,7 @@ static void sde_encoder_phys_cmd_enable(struct sde_encoder_phys *phys_enc)
		SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);

		if (phys_enc->enable_state == SDE_ENC_ENABLED) {
		if (!phys_enc->sde_kms->splash_data.cont_splash_en)
		SDE_ERROR("already enabled\n");
		return;
		}