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Commit f77a1caf authored by Mao Jinlong's avatar Mao Jinlong Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add jtagv8 support for MSM8953 



jtagv8 driver can be used to save and restore debug and ETM
registers across power collapse. Add jtag nodes to support
save/restore ETM registers for MSM8953.

CRs-Fixed: 2230899
Change-Id: I1d61450320a8a79a67b0b9e3ec90bfd7a7ae985d
Signed-off-by: default avatarMao Jinlong <jinlmao@codeaurora.org>
parent c287f849

arch/arm64/boot/dts/qcom/msm8953.dtsi

+97 −0
Original line number Diff line number Diff line
@@ -1322,6 +1322,103 @@ 
			label = "modem";

		};

	};



	jtag_mm0: jtagmm@619c000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x619c000 0x1000>;

		reg-names = "etm-base";



		qcom,coresight-jtagmm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk";

	};



	jtag_mm1: jtagmm@619d000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x619d000 0x1000>;

		reg-names = "etm-base";



		qcom,coresight-jtagmm-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk";

	};



	jtag_mm2: jtagmm@619e000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x619e000 0x1000>;

		reg-names = "etm-base";



		qcom,coresight-jtagmm-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk";

	};



	jtag_mm3: jtagmm@619f000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x619f000 0x1000>;

		reg-names = "etm-base";



		qcom,coresight-jtagmm-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk";

	};



	jtag_mm4: jtagmm@61bc000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x61bc000 0x1000>;

		reg-names = "etm-base";



		qcom,coresight-jtagmm-cpu = <&CPU4>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk";

	};



	jtag_mm5: jtagmm@61bd000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x61bd000 0x1000>;

		reg-names = "etm-base";



		qcom,coresight-jtagmm-cpu = <&CPU5>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk";

	};



	jtag_mm6: jtagmm@61be000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x61be000 0x1000>;

		reg-names = "etm-base";



		qcom,coresight-jtagmm-cpu = <&CPU6>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk";

	};



	jtag_mm7: jtagmm@61bf000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x61bf000 0x1000>;

		reg-names = "etm-base";



		qcom,coresight-jtagmm-cpu = <&CPU7>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk";

	};



		sdcc1_ice: sdcc1ice@7803000 {

		compatible = "qcom,ice";

		reg = <0x7803000 0x8000>;