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Commit f7089d92 authored by Philipp Zabel's avatar Philipp Zabel
Browse files

gpu: ipu-v3: limit pixel clock divider to 8-bits 



The DI pixel clock divider bit field is only 8 bits wide for the
integer part, so limit the divider to the 1...255 interval before
deciding whether the internal clock can be used and before writing
to the register.

Reported-by: default avatarFelix Mellmann <felix.mellmann@gmail.com>
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent 91fd8966

drivers/gpu/ipu-v3/ipu-di.c

+3 −6
Original line number Diff line number Diff line
@@ -441,8 +441,7 @@ static void ipu_di_config_clock(struct ipu_di *di, 


			in_rate = clk_get_rate(clk);

			div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);

			if (div == 0)

				div = 1;

			div = clamp(div, 1U, 255U);



			clkgen0 = div << 4;

		}
@@ -459,8 +458,7 @@ static void ipu_di_config_clock(struct ipu_di *di, 


		clkrate = clk_get_rate(di->clk_ipu);

		div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock);

		if (div == 0)

			div = 1;

		div = clamp(div, 1U, 255U);

		rate = clkrate / div;



		error = rate / (sig->mode.pixelclock / 1000);
@@ -483,8 +481,7 @@ static void ipu_di_config_clock(struct ipu_di *di, 


			in_rate = clk_get_rate(clk);

			div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);

			if (div == 0)

				div = 1;

			div = clamp(div, 1U, 255U);



			clkgen0 = div << 4;

		}