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Commit f6b530ac authored by Clarence Ip's avatar Clarence Ip
Browse files

drm/msm/sde: handle sticky inline rotate flush bit 



The ROT bit of the flush register is only cleared during
frames with inline rotation enabled, so avoid checking its
status unless the CTL is configured for inline rotation.

When re-entering an inline rotation, it is also necessary to
postpone the ctl sbuf mode configuration until after the
rotator hardware has completed setting up the current commit
because a vsync can potentially start the rotator before the
encode kickoff/flush when operating in video mode.

Change-Id: I13641a1e90ed8de5cc1fb51c019c9bad9363041d
Signed-off-by: default avatarClarence Ip <cip@codeaurora.org>
parent d9089f47

drivers/gpu/drm/msm/sde/sde_crtc.c

+8 −4
Original line number Diff line number Diff line
@@ -1360,9 +1360,6 @@ static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc, 
					mixer, &cstate->dim_layer[i]);

	}



	if (ctl->ops.setup_sbuf_cfg)

		ctl->ops.setup_sbuf_cfg(ctl, &cstate->sbuf_cfg);



	_sde_crtc_program_lm_output_roi(crtc);

}
@@ -2230,7 +2227,8 @@ void sde_crtc_commit_kickoff(struct drm_crtc *crtc) 
	struct msm_drm_private *priv;

	struct sde_kms *sde_kms;

	struct sde_crtc_state *cstate;

	int ret;

	struct sde_hw_ctl *ctl;

	int ret, i;



	if (!crtc) {

		SDE_ERROR("invalid argument\n");
@@ -2298,6 +2296,12 @@ void sde_crtc_commit_kickoff(struct drm_crtc *crtc) 
		drm_atomic_crtc_for_each_plane(plane, crtc)

			sde_plane_kickoff(plane);



	for (i = 0; i < sde_crtc->num_mixers; i++) {

		ctl = sde_crtc->mixers[i].hw_ctl;

		if (ctl && ctl->ops.setup_sbuf_cfg)

			ctl->ops.setup_sbuf_cfg(ctl, &cstate->sbuf_cfg);

	}



	sde_vbif_clear_errors(sde_kms);



	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

drivers/gpu/drm/msm/sde/sde_hw_ctl.c

+9 −1
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#define   CTL_ROT_START                 0x0CC



#define CTL_MIXER_BORDER_OUT            BIT(24)

#define CTL_FLUSH_MASK_ROT              BIT(27)

#define CTL_FLUSH_MASK_CTL              BIT(17)



#define SDE_REG_RESET_TIMEOUT_COUNT    20
@@ -123,6 +124,13 @@ static inline void sde_hw_ctl_trigger_flush(struct sde_hw_ctl *ctx) 
static inline u32 sde_hw_ctl_get_flush_register(struct sde_hw_ctl *ctx)

{

	struct sde_hw_blk_reg_map *c = &ctx->hw;

	u32 rot_op_mode;



	rot_op_mode = SDE_REG_READ(c, CTL_ROT_TOP) & 0x3;



	/* rotate flush bit is undefined if offline mode, so ignore it */

	if (rot_op_mode == SDE_CTL_ROT_OP_MODE_OFFLINE)

		return SDE_REG_READ(c, CTL_FLUSH) & ~CTL_FLUSH_MASK_ROT;



	return SDE_REG_READ(c, CTL_FLUSH);

}
@@ -273,7 +281,7 @@ static inline int sde_hw_ctl_get_bitmask_rot(struct sde_hw_ctl *ctx, 
{

	switch (rot) {

	case ROT_0:

		*flushbits |= BIT(27);

		*flushbits |= CTL_FLUSH_MASK_ROT;

		break;

	default:

		return -EINVAL;