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Commit f69e91f2 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Greg Kroah-Hartman
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x86/cpufeatures: Disentangle SSBD enumeration 



commit 52817587e706686fcdb27f14c1b000c92f266c96 upstream

The SSBD enumeration is similarly to the other bits magically shared
between Intel and AMD though the mechanisms are different.

Make X86_FEATURE_SSBD synthetic and set it depending on the vendor specific
features or family dependent setup.

Change the Intel bit to X86_FEATURE_SPEC_CTRL_SSBD to denote that SSBD is
controlled via MSR_SPEC_CTRL and fix up the usage sites.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: default avatarDavid Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a7c34322

arch/x86/include/asm/cpufeatures.h

+3 −2
Original line number Diff line number Diff line
@@ -198,6 +198,7 @@ 
#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */



#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */

#define X86_FEATURE_SSBD	( 7*32+17) /* Speculative Store Bypass Disable */



#define X86_FEATURE_RSB_CTXSW	( 7*32+19) /* "" Fill RSB on context switches */
@@ -207,7 +208,7 @@ 
#define X86_FEATURE_USE_IBPB	( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */

#define X86_FEATURE_USE_IBRS_FW	( 7*32+22) /* "" Use IBRS during runtime firmware calls */

#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */

#define X86_FEATURE_AMD_SSBD	( 7*32+24) /* "" AMD SSBD implementation */

#define X86_FEATURE_LS_CFG_SSBD	( 7*32+24) /* "" AMD SSBD implementation */

#define X86_FEATURE_IBRS	( 7*32+25) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_IBPB	( 7*32+26) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_STIBP	( 7*32+27) /* Single Thread Indirect Branch Predictors */
@@ -314,7 +315,7 @@ 
#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */

#define X86_FEATURE_SSBD		(18*32+31) /* Speculative Store Bypass Disable */

#define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */



/*

 * BUG word(s)

arch/x86/kernel/cpu/amd.c

+1 −6
Original line number Diff line number Diff line
@@ -558,8 +558,8 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 
		 * avoid RMW. If that faults, do not enable SSBD.

		 */

		if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {

			setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);

			setup_force_cpu_cap(X86_FEATURE_SSBD);

			setup_force_cpu_cap(X86_FEATURE_AMD_SSBD);

			x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;

		}

	}
@@ -848,11 +848,6 @@ static void init_amd(struct cpuinfo_x86 *c) 
	/* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */

	if (!cpu_has(c, X86_FEATURE_XENPV))

		set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);



	if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) {

		set_cpu_cap(c, X86_FEATURE_SSBD);

		set_cpu_cap(c, X86_FEATURE_AMD_SSBD);

	}

}



#ifdef CONFIG_X86_32

arch/x86/kernel/cpu/bugs.c

+5 −5
Original line number Diff line number Diff line
@@ -158,8 +158,8 @@ void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl) 
	if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))

		return;



	/* Intel controls SSB in MSR_SPEC_CTRL */

	if (static_cpu_has(X86_FEATURE_SPEC_CTRL))

	/* SSBD controlled in MSR_SPEC_CTRL */

	if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))

		host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);



	if (host != guest_spec_ctrl)
@@ -175,8 +175,8 @@ void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl) 
	if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))

		return;



	/* Intel controls SSB in MSR_SPEC_CTRL */

	if (static_cpu_has(X86_FEATURE_SPEC_CTRL))

	/* SSBD controlled in MSR_SPEC_CTRL */

	if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))

		host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);



	if (host != guest_spec_ctrl)
@@ -188,7 +188,7 @@ static void x86_amd_ssb_disable(void) 
{

	u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;



	if (boot_cpu_has(X86_FEATURE_AMD_SSBD))

	if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))

		wrmsrl(MSR_AMD64_LS_CFG, msrval);

}

arch/x86/kernel/cpu/common.c

+3 −0
Original line number Diff line number Diff line
@@ -735,6 +735,9 @@ static void init_speculation_control(struct cpuinfo_x86 *c) 
	if (cpu_has(c, X86_FEATURE_INTEL_STIBP))

		set_cpu_cap(c, X86_FEATURE_STIBP);



	if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD))

		set_cpu_cap(c, X86_FEATURE_SSBD);



	if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {

		set_cpu_cap(c, X86_FEATURE_IBRS);

		set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);

arch/x86/kernel/cpu/intel.c

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) 
		setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);

		setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);

		setup_clear_cpu_cap(X86_FEATURE_SSBD);

		setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);

	}



	/*