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Commit f5a5c89e authored by Jonathan Austin's avatar Jonathan Austin Committed by Russell King
Browse files

ARM: 8604/1: V7M: Add support for reading the CTR with read_cpuid_cachetype() 



With the addition of caches to the V7M Architecture a new Cache Type
Register (CTR) is defined at 0xE000ED7C. This register serves the same
purpose as the V7A/R version and accessed via the read_cpuid_cachetype.

Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
Signed-off-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: default avatarAndras Szemzo <sza@esh.hu>
Tested-by: default avatarJoachim Eastwood <manabian@gmail.com>
Tested-by: default avatarAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 296909ee

arch/arm/include/asm/cachetype.h

+15 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask) 
#define CSSELR_L6	(5 << 1)

#define CSSELR_L7	(6 << 1)



#ifndef CONFIG_CPU_V7M

static inline void set_csselr(unsigned int cache_selector)

{

	asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
@@ -79,5 +80,19 @@ static inline unsigned int read_ccsidr(void) 
	asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));

	return val;

}

#else /* CONFIG_CPU_V7M */

#include <linux/io.h>

#include "asm/v7m.h"



static inline void set_csselr(unsigned int cache_selector)

{

	writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);

}



static inline unsigned int read_ccsidr(void)

{

	return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);

}

#endif



#endif

arch/arm/include/asm/cputype.h

+10 −5
Original line number Diff line number Diff line
@@ -164,6 +164,11 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) 
	return read_cpuid(CPUID_ID);

}



static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)

{

	return read_cpuid(CPUID_CACHETYPE);

}



#elif defined(CONFIG_CPU_V7M)



static inline unsigned int __attribute_const__ read_cpuid_id(void)
@@ -171,6 +176,11 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) 
	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);

}



static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)

{

	return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);

}



#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */



static inline unsigned int __attribute_const__ read_cpuid_id(void)
@@ -210,11 +220,6 @@ static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void) 
	return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;

}



static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)

{

	return read_cpuid(CPUID_CACHETYPE);

}



static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)

{

	return read_cpuid(CPUID_TCM);

arch/arm/kernel/setup.c

+5 −4
Original line number Diff line number Diff line
@@ -312,11 +312,12 @@ static void __init cacheid_init(void) 
{

	unsigned int arch = cpu_architecture();



	if (arch == CPU_ARCH_ARMv7M) {

		cacheid = 0;

	} else if (arch >= CPU_ARCH_ARMv6) {

	if (arch >= CPU_ARCH_ARMv6) {

		unsigned int cachetype = read_cpuid_cachetype();

		if ((cachetype & (7 << 29)) == 4 << 29) {



		if ((arch == CPU_ARCH_ARMv7M) && !cachetype) {

			cacheid = 0;

		} else if ((cachetype & (7 << 29)) == 4 << 29) {

			/* ARMv7 register format */

			arch = CPU_ARCH_ARMv7;

			cacheid = CACHEID_VIPT_NONALIASING;