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Commit f56a73a1 authored by Dhaval Patel's avatar Dhaval Patel
Browse files

drm/msm/sde: update dim layer color configuration 



The dim layer color is configured on layer mixer and
layer mixer color does not allow to set anything on
lsb two bits. The dim layer configuration also needs
the valid blending selection to update transparency
with lower blend source pipes.

Change-Id: If88cf19cde9d0065b1a7abd040d2203f59e022b3
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 68dfac8e

drivers/gpu/drm/msm/sde/sde_hw_lm.c

+12 −7
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ static inline int _stage_offset(struct sde_hw_mixer *ctx, enum sde_stage stage) 
	if (stage == SDE_STAGE_BASE)

		rc = -EINVAL;

	else if (stage <= sblk->maxblendstages)

		rc = sblk->blendstage_base[stage - 1];

		rc = sblk->blendstage_base[stage - SDE_STAGE_0];

	else

		rc = -EINVAL;
@@ -198,7 +198,7 @@ static void sde_hw_lm_setup_dim_layer(struct sde_hw_mixer *ctx, 
{

	struct sde_hw_blk_reg_map *c = &ctx->hw;

	int stage_off;

	u32 val = 0;

	u32 val = 0, alpha = 0;



	stage_off = _stage_offset(ctx, dim_layer->stage);

	if (stage_off < 0) {
@@ -206,13 +206,13 @@ static void sde_hw_lm_setup_dim_layer(struct sde_hw_mixer *ctx, 
		return;

	}



	val = (dim_layer->color_fill.color_1 & 0xFFF) << 16 |

			(dim_layer->color_fill.color_0 & 0xFFF);

	alpha = dim_layer->color_fill.color_3 & 0xFF;

	val = ((dim_layer->color_fill.color_1 << 2) & 0xFFF) << 16 |

			((dim_layer->color_fill.color_0 << 2) & 0xFFF);

	SDE_REG_WRITE(c, LM_FG_COLOR_FILL_COLOR_0 + stage_off, val);



	val = 0;

	val = (dim_layer->color_fill.color_3 & 0xFFF) << 16 |

			(dim_layer->color_fill.color_2 & 0xFFF);

	val = (alpha << 4) << 16 |

			((dim_layer->color_fill.color_2 << 2) & 0xFFF);

	SDE_REG_WRITE(c, LM_FG_COLOR_FILL_COLOR_1 + stage_off, val);



	val = dim_layer->rect.h << 16 | dim_layer->rect.w;
@@ -222,9 +222,14 @@ static void sde_hw_lm_setup_dim_layer(struct sde_hw_mixer *ctx, 
	SDE_REG_WRITE(c, LM_FG_COLOR_FILL_XY + stage_off, val);



	val = BIT(16); /* enable dim layer */

	val |= SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;

	if (dim_layer->flags & SDE_DRM_DIM_LAYER_EXCLUSIVE)

		val |= BIT(17);

	else

		val &= ~BIT(17);

	SDE_REG_WRITE(c, LM_BLEND0_OP + stage_off, val);

	val = (alpha << 16) | (0xff - alpha);

	SDE_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, val);

}



static void sde_hw_lm_setup_misr(struct sde_hw_mixer *ctx,