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Commit f50a0380 authored by Daniel Mack's avatar Daniel Mack Committed by Tony Lindgren
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ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs 



The am33xx is capable of handling bch error correction modes, so
enable that feature in the driver.

Signed-off-by: default avatarDaniel Mack <zonque@gmail.com>
Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 504f3c6d

arch/arm/mach-omap2/gpmc-nand.c

+5 −4
Original line number Original line Diff line number Diff line
@@ -92,17 +92,18 @@ static int omap2_nand_gpmc_retime( 
static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)

static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)

{

{

	/* support only OMAP3 class */

	/* support only OMAP3 class */

	if (!cpu_is_omap34xx()) {

	if (!cpu_is_omap34xx() && !soc_is_am33xx()) {

		pr_err("BCH ecc is not supported on this CPU\n");

		pr_err("BCH ecc is not supported on this CPU\n");

		return 0;

		return 0;

	}

	}





	/*

	/*

	 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.

	 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1

	 * Other chips may be added if confirmed to work.

	 * and AM33xx derivates. Other chips may be added if confirmed to work.

	 */

	 */

	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&

	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&

	    (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {

	    (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&

	    (!soc_is_am33xx())) {

		pr_err("BCH 4-bit mode is not supported on this CPU\n");

		pr_err("BCH 4-bit mode is not supported on this CPU\n");

		return 0;

		return 0;

	}

	}