Loading drivers/gpu/msm/kgsl_gmu.c +12 −2 Original line number Diff line number Diff line Loading @@ -1662,7 +1662,7 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev, if (!kgsl_gmu_isenabled(KGSL_DEVICE(adreno_dev))) return 0; for (i = 0; i < GMU_WAKEUP_RETRY_MAX; i++) { for (i = 0; i < GMU_LONG_WAKEUP_RETRY_LIMIT; i++) { adreno_read_gmureg(adreno_dev, ADRENO_REG_GMU_AHB_FENCE_STATUS, &status); Loading @@ -1677,9 +1677,19 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev, /* Try to write the fenced register again */ adreno_writereg(adreno_dev, offset, val); if (i == GMU_SHORT_WAKEUP_RETRY_LIMIT) dev_err(adreno_dev->dev.dev, "Waited %d usecs to write fenced register 0x%x. Continuing to wait...\n", (GMU_SHORT_WAKEUP_RETRY_LIMIT * GMU_WAKEUP_DELAY_US), reg_offset); } dev_err(adreno_dev->dev.dev, "GMU fenced register write timed out: reg 0x%x\n", reg_offset); "Timed out waiting %d usecs to write fenced register 0x%x\n", GMU_LONG_WAKEUP_RETRY_LIMIT * GMU_WAKEUP_DELAY_US, reg_offset); return -ETIMEDOUT; } drivers/gpu/msm/kgsl_gmu.h +9 −2 Original line number Diff line number Diff line Loading @@ -92,8 +92,15 @@ * the GMU will start shutting down before we try again. */ #define GMU_WAKEUP_DELAY_US 10 /* Max amount of tries to wake up the GMU. */ #define GMU_WAKEUP_RETRY_MAX 60 /* Max amount of tries to wake up the GMU. The short retry * limit is half of the long retry limit. After the short * number of retries, we print an informational message to say * exiting IFPC is taking longer than expected. We continue * to retry after this until the long retry limit. */ #define GMU_SHORT_WAKEUP_RETRY_LIMIT 100 #define GMU_LONG_WAKEUP_RETRY_LIMIT 200 /* Bits for the flags field in the gmu structure */ enum gmu_flags { Loading Loading
drivers/gpu/msm/kgsl_gmu.c +12 −2 Original line number Diff line number Diff line Loading @@ -1662,7 +1662,7 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev, if (!kgsl_gmu_isenabled(KGSL_DEVICE(adreno_dev))) return 0; for (i = 0; i < GMU_WAKEUP_RETRY_MAX; i++) { for (i = 0; i < GMU_LONG_WAKEUP_RETRY_LIMIT; i++) { adreno_read_gmureg(adreno_dev, ADRENO_REG_GMU_AHB_FENCE_STATUS, &status); Loading @@ -1677,9 +1677,19 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev, /* Try to write the fenced register again */ adreno_writereg(adreno_dev, offset, val); if (i == GMU_SHORT_WAKEUP_RETRY_LIMIT) dev_err(adreno_dev->dev.dev, "Waited %d usecs to write fenced register 0x%x. Continuing to wait...\n", (GMU_SHORT_WAKEUP_RETRY_LIMIT * GMU_WAKEUP_DELAY_US), reg_offset); } dev_err(adreno_dev->dev.dev, "GMU fenced register write timed out: reg 0x%x\n", reg_offset); "Timed out waiting %d usecs to write fenced register 0x%x\n", GMU_LONG_WAKEUP_RETRY_LIMIT * GMU_WAKEUP_DELAY_US, reg_offset); return -ETIMEDOUT; }
drivers/gpu/msm/kgsl_gmu.h +9 −2 Original line number Diff line number Diff line Loading @@ -92,8 +92,15 @@ * the GMU will start shutting down before we try again. */ #define GMU_WAKEUP_DELAY_US 10 /* Max amount of tries to wake up the GMU. */ #define GMU_WAKEUP_RETRY_MAX 60 /* Max amount of tries to wake up the GMU. The short retry * limit is half of the long retry limit. After the short * number of retries, we print an informational message to say * exiting IFPC is taking longer than expected. We continue * to retry after this until the long retry limit. */ #define GMU_SHORT_WAKEUP_RETRY_LIMIT 100 #define GMU_LONG_WAKEUP_RETRY_LIMIT 200 /* Bits for the flags field in the gmu structure */ enum gmu_flags { Loading