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Commit f4c34295 authored by Gopikrishnaiah Anandan's avatar Gopikrishnaiah Anandan Committed by Dhaval Patel
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drm/msm/sde: enable pixel ext and qseed3 along with VIG 



Pixel extension configuration is compulsory for vig pipes
on msmskunk and msm8998 target. If drm client does not provide
the pixel extension and qseed3 configuration, driver should
set the default values. Change sets the default values if
client is not configuring the blocks when VIG pipes are
selected.

Change-Id: I02f0e76fb87587d2eed9e5f4fcca5baa7d605b92
Signed-off-by: default avatarGopikrishnaiah Anandan <agopik@codeaurora.org>
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 1c184922

drivers/gpu/drm/msm/sde/sde_hw_sspp.h

+12 −0
Original line number Diff line number Diff line
@@ -64,6 +64,18 @@ enum sde_hw_filter { 
	SDE_SCALE_FILTER_MAX

};



enum sde_hw_filter_alpa {

	SDE_SCALE_ALPHA_PIXEL_REP,

	SDE_SCALE_ALPHA_BIL

};



enum sde_hw_filter_yuv {

	SDE_SCALE_2D_4X4,

	SDE_SCALE_2D_CIR,

	SDE_SCALE_1D_SEP,

	SDE_SCALE_BIL

};



struct sde_hw_sharp_cfg {

	u32 strength;

	u32 edge_thr;

drivers/gpu/drm/msm/sde/sde_plane.c

+70 −0
Original line number Diff line number Diff line
@@ -60,6 +60,9 @@ 
#define SDE_PLANE_DIRTY_SHARPEN	0x4

#define SDE_PLANE_DIRTY_ALL	0xFFFFFFFF



#define SDE_QSEED3_DEFAULT_PRELOAD_H 0x4

#define SDE_QSEED3_DEFAULT_PRELOAD_V 0x3



/**

 * enum sde_plane_qos - Different qos configurations for each pipe

 *
@@ -615,6 +618,73 @@ static void _sde_plane_setup_scaler3(struct sde_plane *psde, 
		const struct sde_format *fmt,

		uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)

{

	uint32_t decimated, i;



	if (!psde || !scale_cfg || !fmt || !chroma_subsmpl_h ||

			!chroma_subsmpl_v) {

		SDE_ERROR("psde %pK scale_cfg %pK fmt %pK smp_h %d smp_v %d\n"

			, psde, scale_cfg, fmt, chroma_subsmpl_h,

			chroma_subsmpl_v);

		return;

	}



	memset(scale_cfg, 0, sizeof(*scale_cfg));



	decimated = DECIMATED_DIMENSION(src_w,

			psde->pipe_cfg.horz_decimation);

	scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =

		mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);

	decimated = DECIMATED_DIMENSION(src_h,

			psde->pipe_cfg.vert_decimation);

	scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =

		mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);





	scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =

		scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;

	scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =

		scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;



	scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =

		scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];

	scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =

		scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];



	scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =

		scale_cfg->phase_step_x[SDE_SSPP_COMP_0];

	scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =

		scale_cfg->phase_step_y[SDE_SSPP_COMP_0];



	for (i = 0; i < SDE_MAX_PLANES; i++) {

		scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,

				psde->pipe_cfg.horz_decimation);

		scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h,

				psde->pipe_cfg.vert_decimation);

		if (SDE_FORMAT_IS_YUV(fmt))

			scale_cfg->src_width[i] &= ~0x1;

		if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {

			scale_cfg->src_width[i] /= chroma_subsmpl_h;

			scale_cfg->src_height[i] /= chroma_subsmpl_v;

		}

		scale_cfg->preload_x[i] = SDE_QSEED3_DEFAULT_PRELOAD_H;

		scale_cfg->preload_y[i] = SDE_QSEED3_DEFAULT_PRELOAD_V;

		psde->pixel_ext.num_ext_pxls_top[i] =

			scale_cfg->src_height[i];

		psde->pixel_ext.num_ext_pxls_left[i] =

			scale_cfg->src_width[i];

	}

	if (!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)

		&& (src_w == dst_w))

		return;



	scale_cfg->dst_width = dst_w;

	scale_cfg->dst_height = dst_h;

	scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;

	scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;

	scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;

	scale_cfg->lut_flag = 0;

	scale_cfg->blend_cfg = 1;

	scale_cfg->enable = 1;

}



/**