drm/i915: lock down pch pll accouting some more (f4a091c7) · Commits · e / devices / android_kernel_fairphone_FP3

Before I start to make a complete mess out of this, crank up the paranoia level a bit. v2: Kill the has_pch_encoder check in put_shared_dpll - it's invalid as spotted by Ville since we currently only put the dpll when we already have the new pipe config. So a direct pch port -> cpu edp transition will hit this. v3: Now that I've lifted my blinders add the WARN_ON Ville requested. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:

Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:

Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/intel_display.c

+7 −1

Original line number	Diff line number	Diff line
		@@ -1432,6 +1432,7 @@ static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
		assert_pch_pll_enabled(dev_priv, pll, NULL);
		return;
		}
		WARN_ON(pll->on);

		DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);

		@@ -1470,6 +1471,7 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
		}

		assert_pch_pll_enabled(dev_priv, pll, NULL);
		WARN_ON(!pll->on);
		if (--pll->active)
		return;

		@@ -3069,7 +3071,11 @@ static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
		return;
		}

		--pll->refcount;
		if (--pll->refcount == 0) {
		WARN_ON(pll->on);
		WARN_ON(pll->active);
		}

		intel_crtc->pch_pll = NULL;
		}