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Commit f490f326 authored by Nicolin Chen's avatar Nicolin Chen Committed by Mark Brown
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ASoC: fsl_spdif: Don't try to round-up for clock divisor calculation 



As commit 6c8ca30e ("ASoC: fsl_ssi: Don't try to round-up for PM
divisor calculation") mentioned that there's no more need to use a
round up work around to get a better divisor since the clk-divider
driver has been refined a lot.

So this patch applies the same modification to fsl_spdif driver.

Signed-off-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent b787f68c

sound/soc/fsl/fsl_spdif.c

+4 −6
Original line number Original line Diff line number Diff line
@@ -417,11 +417,9 @@ static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 
	if (clk != STC_TXCLK_SPDIF_ROOT)

	if (clk != STC_TXCLK_SPDIF_ROOT)

		goto clk_set_bypass;

		goto clk_set_bypass;





	/*

	/* The S/PDIF block needs a clock of 64 * fs * txclk_df */

	 * The S/PDIF block needs a clock of 64 * fs * txclk_df.

	ret = clk_set_rate(spdif_priv->txclk[rate],

	 * So request 64 * fs * (txclk_df + 1) to get rounded.

			   64 * sample_rate * txclk_df);

	 */

	ret = clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (txclk_df + 1));

	if (ret) {

	if (ret) {

		dev_err(&pdev->dev, "failed to set tx clock rate\n");

		dev_err(&pdev->dev, "failed to set tx clock rate\n");

		return ret;

		return ret;
@@ -1060,7 +1058,7 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 




	for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {

	for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {

		for (txclk_df = 1; txclk_df <= 128; txclk_df++) {

		for (txclk_df = 1; txclk_df <= 128; txclk_df++) {

			rate_ideal = rate[index] * (txclk_df + 1) * 64;

			rate_ideal = rate[index] * txclk_df * 64;

			if (round)

			if (round)

				rate_actual = clk_round_rate(clk, rate_ideal);

				rate_actual = clk_round_rate(clk, rate_ideal);

			else

			else