Merge branches 'x86/amd', 'x86/vt-d', 'arm/exynos', 'arm/mediatek', 'arm/msm',...

* ARM SMMUv3 Architecture Implementation

The SMMUv3 architecture is a significant deparature from previous

The SMMUv3 architecture is a significant departure from previous

revisions, replacing the MMIO register interface with in-memory command

and event queues and adding support for the ATS and PRI components of

the PCIe specification.

* Mediatek IOMMU Architecture Implementation

  Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U) which

uses the ARM Short-Descriptor translation table format for address translation.

  Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and

this M4U have two generations of HW architecture. Generation one uses flat

pagetable, and only supports 4K size page mapping. Generation two uses the

ARM Short-Descriptor translation table format for address translation.

  About the M4U Hardware Block Diagram, please check below:

video decode local arbiter, all these ports are according to the video HW.

Required properties:

- compatible : must be "mediatek,mt8173-m4u".

- compatible : must be one of the following string:

	"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.

	"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.

- reg : m4u register base and size.

- interrupts : the interrupt of m4u.

- clocks : must contain one entry for each clock-names.

	according to the local arbiter index, like larb0, larb1, larb2...

- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.

	Specifies the mtk_m4u_id as defined in

	dt-binding/memory/mt8173-larb-port.h.

	dt-binding/memory/mt2701-larb-port.h for mt2701 and

	dt-binding/memory/mt8173-larb-port.h for mt8173

Example:

	iommu: iommu@10205000 {

* QCOM IOMMU

The MSM IOMMU is an implementation compatible with the ARM VMSA short

descriptor page tables. It provides address translation for bus masters outside

of the CPU, each connected to the IOMMU through a port called micro-TLB.

Required Properties:

  - compatible: Must contain "qcom,apq8064-iommu".

  - reg: Base address and size of the IOMMU registers.

  - interrupts: Specifiers for the MMU fault interrupts. For instances that

    support secure mode two interrupts must be specified, for non-secure and

    secure mode, in that order. For instances that don't support secure mode a

    single interrupt must be specified.

  - #iommu-cells: The number of cells needed to specify the stream id. This

		  is always 1.

  - qcom,ncb:	  The total number of context banks in the IOMMU.

  - clocks	: List of clocks to be used during SMMU register access. See

		  Documentation/devicetree/bindings/clock/clock-bindings.txt

		  for information about the format. For each clock specified

		  here, there must be a corresponding entry in clock-names

		  (see below).

  - clock-names	: List of clock names corresponding to the clocks specified in

		  the "clocks" property (above).

		  Should be "smmu_pclk" for specifying the interface clock

		  required for iommu's register accesses.

		  Should be "smmu_clk" for specifying the functional clock

		  required by iommu for bus accesses.

Each bus master connected to an IOMMU must reference the IOMMU in its device

node with the following property:

  - iommus: A reference to the IOMMU in multiple cells. The first cell is a

	    phandle to the IOMMU and the second cell is the stream id.

	    A single master device can be connected to more than one iommu

	    and multiple contexts in each of the iommu. So multiple entries

	    are required to list all the iommus and the stream ids that the

	    master is connected to.

Example: mdp iommu and its bus master

                mdp_port0: iommu@7500000 {

			compatible = "qcom,apq8064-iommu";

			#iommu-cells = <1>;

			clock-names =

			    "smmu_pclk",

			    "smmu_clk";

			clocks =

			    <&mmcc SMMU_AHB_CLK>,

			    <&mmcc MDP_AXI_CLK>;

			reg = <0x07500000 0x100000>;

			interrupts =

			    <GIC_SPI 63 0>,

			    <GIC_SPI 64 0>;

			qcom,ncb = <2>;

		};

		mdp: qcom,mdp@5100000 {

			compatible = "qcom,mdp";

			...

			iommus = <&mdp_port0 0

				  &mdp_port0 2>;

		};

The hardware block diagram please check bindings/iommu/mediatek,iommu.txt

Mediatek SMI have two generations of HW architecture, mt8173 uses the second

generation of SMI HW while mt2701 uses the first generation HW of SMI.

There's slight differences between the two SMI, for generation 2, the

register which control the iommu port is at each larb's register base. But

for generation 1, the register is at smi ao base(smi always on register

base). Besides that, the smi async clock should be prepared and enabled for

SMI generation 1 to transform the smi clock into emi clock domain, but that is

not needed for SMI generation 2.

Required properties:

- compatible : must be "mediatek,mt8173-smi-common"

- compatible : must be one of :

	"mediatek,mt2701-smi-common"

	"mediatek,mt8173-smi-common"

- reg : the register and size of the SMI block.

- power-domains : a phandle to the power domain of this local arbiter.

- clocks : Must contain an entry for each entry in clock-names.

- clock-names : must contain 2 entries, as follows:

- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries

  for generation 2 smi HW as follows:

  - "apb" : Advanced Peripheral Bus clock, It's the clock for setting

	    the register.

  - "smi" : It's the clock for transfer data and command.

	    They may be the same if both source clocks are the same.

  - "async" : asynchronous clock, it help transform the smi clock into the emi

	      clock domain, this clock is only needed by generation 1 smi HW.

Example:

	smi_common: smi@14022000 {

The hardware block diagram please check bindings/iommu/mediatek,iommu.txt

Required properties:

- compatible : must be "mediatek,mt8173-smi-larb"

- compatible : must be one of :

		"mediatek,mt8173-smi-larb"

		"mediatek,mt2701-smi-larb"

- reg : the register and size of this local arbiter.

- mediatek,smi : a phandle to the smi_common node.

- power-domains : a phandle to the power domain of this local arbiter.