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Commit f3287a52 authored by Alban Bedel's avatar Alban Bedel Committed by Vinod Koul
Browse files

dmaengine: PL08x: Fix reading the byte count in cctl 



There are more fields than just SWIDTH in CH_CONTROL register, so read
register value must be masked in addition to shifting.

Signed-off-by: default avatarAlban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: default avatarTomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent 5110e51d

drivers/dma/amba-pl08x.c

+4 −0
Original line number Diff line number Diff line
@@ -480,6 +480,8 @@ static inline u32 get_bytes_in_cctl(u32 cctl) 
	/* The source width defines the number of bytes */

	u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;



	cctl &= PL080_CONTROL_SWIDTH_MASK;



	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {

	case PL080_WIDTH_8BIT:

		break;
@@ -498,6 +500,8 @@ static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1) 
	/* The source width defines the number of bytes */

	u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;



	cctl &= PL080_CONTROL_SWIDTH_MASK;



	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {

	case PL080_WIDTH_8BIT:

		break;