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Commit f2d4e05a authored by George Shen's avatar George Shen Committed by Kyle Piefer
Browse files

msm: kgsl: Ensure GPU idles before power collapsing it 



Fixes a bug that resulted in powering off the GPUCC domain
before the GMU was ready for power collapse.

CRs-Fixed: 2017390
Change-Id: I193a63c2eed73d6cb7d4fa019ecba3ee10a728ee
Signed-off-by: default avatarGeorge Shen <sqiao@codeaurora.org>
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent ff3d7de3

drivers/gpu/msm/a6xx_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -798,7 +798,7 @@ 
#define A6XX_GMU_GPU_NAP_CTRL			0x1F8E4

#define A6XX_GMU_RPMH_CTRL			0x1F8E8

#define A6XX_GMU_RPMH_HYST_CTRL			0x1F8E9

#define A6XX_GMU_RPMH_POWER_STATE		0x1F8EC

#define A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE    0x1F8EC

#define A6XX_GMU_BOOT_KMD_LM_HANDSHAKE		0x1F9F0



/* HFI registers*/

drivers/gpu/msm/adreno_a6xx.c

+3 −2
Original line number Diff line number Diff line
@@ -1215,7 +1215,8 @@ static int a6xx_notify_slumber(struct kgsl_device *device) 
	if (ret)

		dev_err(&gmu->pdev->dev, "OOB set for slumber timed out\n");

	else {

		kgsl_gmu_regread(device, A6XX_GMU_RPMH_POWER_STATE, &state);

		kgsl_gmu_regread(device,

			A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE, &state);

		if (state != GPU_HW_SLUMBER) {

			dev_err(&gmu->pdev->dev,

					"Failed to prepare for slumber\n");
@@ -2251,7 +2252,7 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_GMU_HFI_SFR_ADDR,

				A6XX_GMU_HFI_SFR_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_RPMH_POWER_STATE,

				A6XX_GMU_RPMH_POWER_STATE),

				A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_GMU2HOST_INTR_CLR,

				A6XX_GMU_GMU2HOST_INTR_CLR),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_GMU2HOST_INTR_INFO,

drivers/gpu/msm/kgsl_gmu.c

+9 −14
Original line number Diff line number Diff line
@@ -1332,12 +1332,6 @@ int gmu_start(struct kgsl_device *device) 
	 * In v2, this function call shall move ahead

	 * of hfi_start() to save power.

	 */

	ret = gpudev->oob_set(adreno_dev, OOB_CPINIT_SET_MASK,

			OOB_CPINIT_CHECK_MASK, OOB_CPINIT_CLEAR_MASK);

	gpudev->oob_clear(adreno_dev, OOB_CPINIT_CLEAR_MASK);



	if (ret)

		goto error_gpu;



	if (device->state == KGSL_STATE_INIT ||

			device->state == KGSL_STATE_SUSPEND) {
@@ -1379,20 +1373,21 @@ void gmu_stop(struct kgsl_device *device) 
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	unsigned long t;

	bool idle = false;

	unsigned int reg;



	if (!test_bit(GMU_CLK_ON, &gmu->flags))

		return;



	if (gpudev->hw_isidle) {

	t = jiffies + msecs_to_jiffies(GMU_IDLE_TIMEOUT);

	while (!time_after(jiffies, t)) {

			if (gpudev->hw_isidle(adreno_dev)) {

		adreno_read_gmureg(ADRENO_DEVICE(device),

			ADRENO_REG_GMU_RPMH_POWER_STATE, &reg);

		if (reg == device->gmu.idle_level) {

			idle = true;

			break;

		}

		cpu_relax();

	}

	}



	gpudev->rpmh_gpu_pwrctrl(adreno_dev, GMU_NOTIFY_SLUMBER, 0, 0);