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Commit f275ac7f authored by Rex Zhu's avatar Rex Zhu Committed by Greg Kroah-Hartman
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drm/amd/powerplay: fix vce cg logic error on CZ/St. 




[ Upstream commit 3731d12dce83d47b357753ffc450ce03f1b49688 ]

can fix Bug 191281: vce ib test failed.

when vce idle, set vce clock gate, so the clock
in vce domain will be disabled.
when need to encode, disable vce clock gate,
enable the clocks to vce engine.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSasha Levin <alexander.levin@verizon.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 77e82094

drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c

+2 −2
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) 
				cgs_set_clockgating_state(

							hwmgr->device,

							AMD_IP_BLOCK_TYPE_VCE,

							AMD_CG_STATE_UNGATE);

							AMD_CG_STATE_GATE);

				cgs_set_powergating_state(

							hwmgr->device,

							AMD_IP_BLOCK_TYPE_VCE,
@@ -218,7 +218,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) 
				cgs_set_clockgating_state(

							hwmgr->device,

							AMD_IP_BLOCK_TYPE_VCE,

							AMD_PG_STATE_GATE);

							AMD_PG_STATE_UNGATE);

				cz_dpm_update_vce_dpm(hwmgr);

				cz_enable_disable_vce_dpm(hwmgr, true);

				return 0;