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Commit f19637e7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull radeon fixes from Dave Airlie:
 "I got these late last week, the main chunks of these fix a rendering
  regression since 3.7, and the settle ones all fix the issue where we
  don't wait long enough for the memory controller to settle after
  turning it off which causes bad memory reads, they all fix real users
  bugs, and most of them are destined for stable.

  Can't remember if you had net connection on that island :-)"

I don't know if the "two tin-cans and a string" thing here on "that
island" can really be considered internet, but I guess I can pull
things.  Barely.

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/radeon: switch back to the CP ring for VM PT updates
  drm/radeon: prevent crash in the ring space allocation
  drm/radeon: Calling object_unrefer() when creating fb failure
  drm/radeon/r5xx-r7xx: wait for the MC to settle after MC blackout
  drm/radeon/evergreen+: wait for the MC to settle after MC blackout
  drm/radeon: protect against div by 0 in backend setup
  drm/radeon: fix backend map setup on 1 RB sumo boards
  drm/radeon: add quirk for RV100 board
  drm/radeon: add WAIT_UNTIL to the non-VM safe regs list for cayman/TN
  drm/radeon: fix MC blackout on evergreen+
parents 8b31849a 089c71a7

drivers/gpu/drm/radeon/evergreen.c

+24 −3
Original line number Diff line number Diff line
@@ -1313,14 +1313,18 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav 
				if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {

					radeon_wait_for_vblank(rdev, i);

					tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;

					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

					WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

				}

			} else {

				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

				if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {

					radeon_wait_for_vblank(rdev, i);

					tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;

					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

					WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

				}

			}

			/* wait for the next frame */
@@ -1345,6 +1349,8 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav 
		blackout &= ~BLACKOUT_MODE_MASK;

		WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);

	}

	/* wait for the MC to settle */

	udelay(100);

}



void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -1378,11 +1384,15 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s 
			if (ASIC_IS_DCE6(rdev)) {

				tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);

				tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;

				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

				WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

			} else {

				tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

				tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;

				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

				WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

			}

			/* wait for the next frame */

			frame_count = radeon_get_vblank_counter(rdev, i);
@@ -2036,9 +2046,20 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	WREG32(HDP_ADDR_CONFIG, gb_addr_config);

	WREG32(DMA_TILING_CONFIG, gb_addr_config);



	if ((rdev->config.evergreen.max_backends == 1) &&

	    (rdev->flags & RADEON_IS_IGP)) {

		if ((disabled_rb_mask & 3) == 1) {

			/* RB0 disabled, RB1 enabled */

			tmp = 0x11111111;

		} else {

			/* RB1 disabled, RB0 enabled */

			tmp = 0x00000000;

		}

	} else {

		tmp = gb_addr_config & NUM_PIPES_MASK;

		tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,

						EVERGREEN_MAX_BACKENDS, disabled_rb_mask);

	}

	WREG32(GB_BACKEND_MAP, tmp);



	WREG32(CGTS_SYS_TCC_DISABLE, 0);

drivers/gpu/drm/radeon/r600.c

+5 −2
Original line number Diff line number Diff line
@@ -1462,12 +1462,15 @@ u32 r6xx_remap_render_backend(struct radeon_device *rdev, 
			      u32 disabled_rb_mask)

{

	u32 rendering_pipe_num, rb_num_width, req_rb_num;

	u32 pipe_rb_ratio, pipe_rb_remain;

	u32 pipe_rb_ratio, pipe_rb_remain, tmp;

	u32 data = 0, mask = 1 << (max_rb_num - 1);

	unsigned i, j;



	/* mask out the RBs that don't exist on that asic */

	disabled_rb_mask |= (0xff << max_rb_num) & 0xff;

	tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);

	/* make sure at least one RB is available */

	if ((tmp & 0xff) != 0xff)

		disabled_rb_mask = tmp;



	rendering_pipe_num = 1 << tiling_pipe_num;

	req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);

drivers/gpu/drm/radeon/radeon_asic.c

+3 −3
Original line number Diff line number Diff line
@@ -1445,7 +1445,7 @@ static struct radeon_asic cayman_asic = { 
	.vm = {

		.init = &cayman_vm_init,

		.fini = &cayman_vm_fini,

		.pt_ring_index = R600_RING_TYPE_DMA_INDEX,

		.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,

		.set_page = &cayman_vm_set_page,

	},

	.ring = {
@@ -1572,7 +1572,7 @@ static struct radeon_asic trinity_asic = { 
	.vm = {

		.init = &cayman_vm_init,

		.fini = &cayman_vm_fini,

		.pt_ring_index = R600_RING_TYPE_DMA_INDEX,

		.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,

		.set_page = &cayman_vm_set_page,

	},

	.ring = {
@@ -1699,7 +1699,7 @@ static struct radeon_asic si_asic = { 
	.vm = {

		.init = &si_vm_init,

		.fini = &si_vm_fini,

		.pt_ring_index = R600_RING_TYPE_DMA_INDEX,

		.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,

		.set_page = &si_vm_set_page,

	},

	.ring = {

drivers/gpu/drm/radeon/radeon_combios.c

+8 −0
Original line number Diff line number Diff line
@@ -2470,6 +2470,14 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 
								   1),

								  ATOM_DEVICE_CRT1_SUPPORT);

				}

				/* RV100 board with external TDMS bit mis-set.

				 * Actually uses internal TMDS, clear the bit.

				 */

				if (dev->pdev->device == 0x5159 &&

				    dev->pdev->subsystem_vendor == 0x1014 &&

				    dev->pdev->subsystem_device == 0x029A) {

					tmp &= ~(1 << 4);

				}

				if ((tmp >> 4) & 0x1) {

					devices |= ATOM_DEVICE_DFP2_SUPPORT;

					radeon_add_legacy_encoder(dev,

drivers/gpu/drm/radeon/radeon_display.c

+3 −1
Original line number Diff line number Diff line
@@ -1115,8 +1115,10 @@ radeon_user_framebuffer_create(struct drm_device *dev, 
	}



	radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);

	if (radeon_fb == NULL)

	if (radeon_fb == NULL) {

		drm_gem_object_unreference_unlocked(obj);

		return ERR_PTR(-ENOMEM);

	}



	ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);

	if (ret) {