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Commit f1949ea0 authored by Lee Jones's avatar Lee Jones Committed by Arnd Bergmann
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ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree 



This provides PL310 Level 2 Cache Controller Device Tree
support for all u8500 based devices.

Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 4905af0e

arch/arm/boot/dts/db8500.dtsi

+8 −0
Original line number Original line Diff line number Diff line
@@ -29,6 +29,14 @@ 
			      <0xa0410100 0x100>;

			      <0xa0410100 0x100>;

		};

		};





		L2: l2-cache {

			compatible = "arm,pl310-cache";

			reg = <0xa0412000 0x1000>;

			interrupts = <0 13 4>;

			cache-unified;

			cache-level = <2>;

		};



		pmu {

		pmu {

			compatible = "arm,cortex-a9-pmu";

			compatible = "arm,cortex-a9-pmu";

			interrupts = <0 7 0x4>;

			interrupts = <0 7 0x4>;

arch/arm/mach-ux500/cache-l2x0.c

+6 −1
Original line number Original line Diff line number Diff line
@@ -5,6 +5,8 @@ 
 */

 */





#include <linux/io.h>

#include <linux/io.h>

#include <linux/of.h>



#include <asm/cacheflush.h>

#include <asm/cacheflush.h>

#include <asm/hardware/cache-l2x0.h>

#include <asm/hardware/cache-l2x0.h>

#include <mach/hardware.h>

#include <mach/hardware.h>
@@ -45,6 +47,9 @@ static int __init ux500_l2x0_init(void) 
	ux500_l2x0_unlock();

	ux500_l2x0_unlock();





	/* 64KB way size, 8 way associativity, force WA */

	/* 64KB way size, 8 way associativity, force WA */

	if (of_have_populated_dt())

		l2x0_of_init(0x3e060000, 0xc0000fff);

	else

		l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);

		l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);





	/*

	/*