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Commit f0c39113 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS update from Ralf Baechle:
 "To avoid unnecessary risk and work the preemption fixes are combined
  with some preparatory work that isn't strictly required.  So it's
  really just 3 fixes:

   - Get is_compat_task() to do the right thing while simplifying it.
     The unnecessary complexity hid a rarely striking bug which could be
     triggered by ext3/ext4 under certain circumstances.
   - Resolve a preemption issue in the irqflags.h functions for kernels
     built to support pre-MIPS32 / pre-MIPS64 Release 2 processors.
   - Fix the interrupt number of the MIPS Malta's CBUS UART."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Malta: Fix interupt number of CBUS UART.
  MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpus
  MIPS: Remove irqflags.h dependency from bitops.h
  MIPS: bitops.h: Change use of 'unsigned short' to 'int'
  MIPS: compat: Delete now unused TIF_32BIT.
  MIPS: compat: Implement is_compat_task() by testing for 32-bit address space.
  MIPS: compat: Fix use of TIF_32BIT_ADDR vs _TIF_32BIT_ADDR
parents 1e096209 225ae5fd

arch/mips/cavium-octeon/executive/cvmx-l2c.c

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
 * measurement, and debugging facilities.

 */



#include <linux/irqflags.h>

#include <asm/octeon/cvmx.h>

#include <asm/octeon/cvmx-l2c.h>

#include <asm/octeon/cvmx-spinlock.h>

arch/mips/include/asm/bitops.h

+39 −89
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ 
#endif



#include <linux/compiler.h>

#include <linux/irqflags.h>

#include <linux/types.h>

#include <asm/barrier.h>

#include <asm/byteorder.h>		/* sigh ... */
@@ -44,6 +43,24 @@ 
#define smp_mb__before_clear_bit()	smp_mb__before_llsc()

#define smp_mb__after_clear_bit()	smp_llsc_mb()





/*

 * These are the "slower" versions of the functions and are in bitops.c.

 * These functions call raw_local_irq_{save,restore}().

 */

void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);

void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);

void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);

int __mips_test_and_set_bit(unsigned long nr,

			    volatile unsigned long *addr);

int __mips_test_and_set_bit_lock(unsigned long nr,

				 volatile unsigned long *addr);

int __mips_test_and_clear_bit(unsigned long nr,

			      volatile unsigned long *addr);

int __mips_test_and_change_bit(unsigned long nr,

			       volatile unsigned long *addr);





/*

 * set_bit - Atomically set a bit in memory

 * @nr: the bit to set
@@ -57,7 +74,7 @@ 
static inline void set_bit(unsigned long nr, volatile unsigned long *addr)

{

	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

	unsigned short bit = nr & SZLONG_MASK;

	int bit = nr & SZLONG_MASK;

	unsigned long temp;



	if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -92,17 +109,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 
			: "=&r" (temp), "+m" (*m)

			: "ir" (1UL << bit));

		} while (unlikely(!temp));

	} else {

		volatile unsigned long *a = addr;

		unsigned long mask;

		unsigned long flags;



		a += nr >> SZLONG_LOG;

		mask = 1UL << bit;

		raw_local_irq_save(flags);

		*a |= mask;

		raw_local_irq_restore(flags);

	}

	} else

		__mips_set_bit(nr, addr);

}



/*
@@ -118,7 +126,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 
static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)

{

	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);

	unsigned short bit = nr & SZLONG_MASK;

	int bit = nr & SZLONG_MASK;

	unsigned long temp;



	if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -153,17 +161,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 
			: "=&r" (temp), "+m" (*m)

			: "ir" (~(1UL << bit)));

		} while (unlikely(!temp));

	} else {

		volatile unsigned long *a = addr;

		unsigned long mask;

		unsigned long flags;



		a += nr >> SZLONG_LOG;

		mask = 1UL << bit;

		raw_local_irq_save(flags);

		*a &= ~mask;

		raw_local_irq_restore(flags);

	}

	} else

		__mips_clear_bit(nr, addr);

}



/*
@@ -191,7 +190,7 @@ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *ad 
 */

static inline void change_bit(unsigned long nr, volatile unsigned long *addr)

{

	unsigned short bit = nr & SZLONG_MASK;

	int bit = nr & SZLONG_MASK;



	if (kernel_uses_llsc && R10000_LLSC_WAR) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -220,17 +219,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) 
			: "=&r" (temp), "+m" (*m)

			: "ir" (1UL << bit));

		} while (unlikely(!temp));

	} else {

		volatile unsigned long *a = addr;

		unsigned long mask;

		unsigned long flags;



		a += nr >> SZLONG_LOG;

		mask = 1UL << bit;

		raw_local_irq_save(flags);

		*a ^= mask;

		raw_local_irq_restore(flags);

	}

	} else

		__mips_change_bit(nr, addr);

}



/*
@@ -244,7 +234,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) 
static inline int test_and_set_bit(unsigned long nr,

	volatile unsigned long *addr)

{

	unsigned short bit = nr & SZLONG_MASK;

	int bit = nr & SZLONG_MASK;

	unsigned long res;



	smp_mb__before_llsc();
@@ -281,18 +271,8 @@ static inline int test_and_set_bit(unsigned long nr, 
		} while (unlikely(!res));



		res = temp & (1UL << bit);

	} else {

		volatile unsigned long *a = addr;

		unsigned long mask;

		unsigned long flags;



		a += nr >> SZLONG_LOG;

		mask = 1UL << bit;

		raw_local_irq_save(flags);

		res = (mask & *a);

		*a |= mask;

		raw_local_irq_restore(flags);

	}

	} else

		res = __mips_test_and_set_bit(nr, addr);



	smp_llsc_mb();
@@ -310,7 +290,7 @@ static inline int test_and_set_bit(unsigned long nr, 
static inline int test_and_set_bit_lock(unsigned long nr,

	volatile unsigned long *addr)

{

	unsigned short bit = nr & SZLONG_MASK;

	int bit = nr & SZLONG_MASK;

	unsigned long res;



	if (kernel_uses_llsc && R10000_LLSC_WAR) {
@@ -345,18 +325,8 @@ static inline int test_and_set_bit_lock(unsigned long nr, 
		} while (unlikely(!res));



		res = temp & (1UL << bit);

	} else {

		volatile unsigned long *a = addr;

		unsigned long mask;

		unsigned long flags;



		a += nr >> SZLONG_LOG;

		mask = 1UL << bit;

		raw_local_irq_save(flags);

		res = (mask & *a);

		*a |= mask;

		raw_local_irq_restore(flags);

	}

	} else

		res = __mips_test_and_set_bit_lock(nr, addr);



	smp_llsc_mb();
@@ -373,7 +343,7 @@ static inline int test_and_set_bit_lock(unsigned long nr, 
static inline int test_and_clear_bit(unsigned long nr,

	volatile unsigned long *addr)

{

	unsigned short bit = nr & SZLONG_MASK;

	int bit = nr & SZLONG_MASK;

	unsigned long res;



	smp_mb__before_llsc();
@@ -428,18 +398,8 @@ static inline int test_and_clear_bit(unsigned long nr, 
		} while (unlikely(!res));



		res = temp & (1UL << bit);

	} else {

		volatile unsigned long *a = addr;

		unsigned long mask;

		unsigned long flags;



		a += nr >> SZLONG_LOG;

		mask = 1UL << bit;

		raw_local_irq_save(flags);

		res = (mask & *a);

		*a &= ~mask;

		raw_local_irq_restore(flags);

	}

	} else

		res = __mips_test_and_clear_bit(nr, addr);



	smp_llsc_mb();
@@ -457,7 +417,7 @@ static inline int test_and_clear_bit(unsigned long nr, 
static inline int test_and_change_bit(unsigned long nr,

	volatile unsigned long *addr)

{

	unsigned short bit = nr & SZLONG_MASK;

	int bit = nr & SZLONG_MASK;

	unsigned long res;



	smp_mb__before_llsc();
@@ -494,18 +454,8 @@ static inline int test_and_change_bit(unsigned long nr, 
		} while (unlikely(!res));



		res = temp & (1UL << bit);

	} else {

		volatile unsigned long *a = addr;

		unsigned long mask;

		unsigned long flags;



		a += nr >> SZLONG_LOG;

		mask = 1UL << bit;

		raw_local_irq_save(flags);

		res = (mask & *a);

		*a ^= mask;

		raw_local_irq_restore(flags);

	}

	} else

		res = __mips_test_and_change_bit(nr, addr);



	smp_llsc_mb();

arch/mips/include/asm/compat.h

+1 −1
Original line number Diff line number Diff line
@@ -290,7 +290,7 @@ struct compat_shmid64_ds { 


static inline int is_compat_task(void)

{

	return test_thread_flag(TIF_32BIT);

	return test_thread_flag(TIF_32BIT_ADDR);

}



#endif /* _ASM_COMPAT_H */

arch/mips/include/asm/io.h

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/compiler.h>

#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/irqflags.h>



#include <asm/addrspace.h>

#include <asm/bug.h>

arch/mips/include/asm/irqflags.h

+75 −132
Original line number Diff line number Diff line
@@ -16,83 +16,13 @@ 
#include <linux/compiler.h>

#include <asm/hazards.h>



__asm__(

	"	.macro	arch_local_irq_enable				\n"

	"	.set	push						\n"

	"	.set	reorder						\n"

	"	.set	noat						\n"

#ifdef CONFIG_MIPS_MT_SMTC

	"	mfc0	$1, $2, 1	# SMTC - clear TCStatus.IXMT	\n"

	"	ori	$1, 0x400					\n"

	"	xori	$1, 0x400					\n"

	"	mtc0	$1, $2, 1					\n"

#elif defined(CONFIG_CPU_MIPSR2)

	"	ei							\n"

#else

	"	mfc0	$1,$12						\n"

	"	ori	$1,0x1f						\n"

	"	xori	$1,0x1e						\n"

	"	mtc0	$1,$12						\n"

#endif

	"	irq_enable_hazard					\n"

	"	.set	pop						\n"

	"	.endm");

#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC)



extern void smtc_ipi_replay(void);



static inline void arch_local_irq_enable(void)

{

#ifdef CONFIG_MIPS_MT_SMTC

	/*

	 * SMTC kernel needs to do a software replay of queued

	 * IPIs, at the cost of call overhead on each local_irq_enable()

	 */

	smtc_ipi_replay();

#endif

	__asm__ __volatile__(

		"arch_local_irq_enable"

		: /* no outputs */

		: /* no inputs */

		: "memory");

}





/*

 * For cli() we have to insert nops to make sure that the new value

 * has actually arrived in the status register before the end of this

 * macro.

 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs

 * no nops at all.

 */

/*

 * For TX49, operating only IE bit is not enough.

 *

 * If mfc0 $12 follows store and the mfc0 is last instruction of a

 * page and fetching the next instruction causes TLB miss, the result

 * of the mfc0 might wrongly contain EXL bit.

 *

 * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008

 *

 * Workaround: mask EXL bit of the result or place a nop before mfc0.

 */

__asm__(

	"	.macro	arch_local_irq_disable\n"

	"	.set	push						\n"

	"	.set	noat						\n"

#ifdef CONFIG_MIPS_MT_SMTC

	"	mfc0	$1, $2, 1					\n"

	"	ori	$1, 0x400					\n"

	"	.set	noreorder					\n"

	"	mtc0	$1, $2, 1					\n"

#elif defined(CONFIG_CPU_MIPSR2)

	"	di							\n"

#else

	"	mfc0	$1,$12						\n"

	"	ori	$1,0x1f						\n"

	"	xori	$1,0x1f						\n"

	"	.set	noreorder					\n"

	"	mtc0	$1,$12						\n"

#endif

	"	irq_disable_hazard					\n"

	"	.set	pop						\n"

	"	.endm							\n");
@@ -106,46 +36,14 @@ static inline void arch_local_irq_disable(void) 
		: "memory");

}



__asm__(

	"	.macro	arch_local_save_flags flags			\n"

	"	.set	push						\n"

	"	.set	reorder						\n"

#ifdef CONFIG_MIPS_MT_SMTC

	"	mfc0	\\flags, $2, 1					\n"

#else

	"	mfc0	\\flags, $12					\n"

#endif

	"	.set	pop						\n"

	"	.endm							\n");



static inline unsigned long arch_local_save_flags(void)

{

	unsigned long flags;

	asm volatile("arch_local_save_flags %0" : "=r" (flags));

	return flags;

}



__asm__(

	"	.macro	arch_local_irq_save result			\n"

	"	.set	push						\n"

	"	.set	reorder						\n"

	"	.set	noat						\n"

#ifdef CONFIG_MIPS_MT_SMTC

	"	mfc0	\\result, $2, 1					\n"

	"	ori	$1, \\result, 0x400				\n"

	"	.set	noreorder					\n"

	"	mtc0	$1, $2, 1					\n"

	"	andi	\\result, \\result, 0x400			\n"

#elif defined(CONFIG_CPU_MIPSR2)

	"	di	\\result					\n"

	"	andi	\\result, 1					\n"

#else

	"	mfc0	\\result, $12					\n"

	"	ori	$1, \\result, 0x1f				\n"

	"	xori	$1, 0x1f					\n"

	"	.set	noreorder					\n"

	"	mtc0	$1, $12						\n"

#endif

	"	irq_disable_hazard					\n"

	"	.set	pop						\n"

	"	.endm							\n");
@@ -160,19 +58,13 @@ static inline unsigned long arch_local_irq_save(void) 
	return flags;

}





__asm__(

	"	.macro	arch_local_irq_restore flags			\n"

	"	.set	push						\n"

	"	.set	noreorder					\n"

	"	.set	noat						\n"

#ifdef CONFIG_MIPS_MT_SMTC

	"mfc0	$1, $2, 1						\n"

	"andi	\\flags, 0x400						\n"

	"ori	$1, 0x400						\n"

	"xori	$1, 0x400						\n"

	"or	\\flags, $1						\n"

	"mtc0	\\flags, $2, 1						\n"

#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)

#if defined(CONFIG_IRQ_CPU)

	/*

	 * Slow, but doesn't suffer from a relatively unlikely race

	 * condition we're having since days 1.
@@ -181,40 +73,22 @@ __asm__( 
	"	di							\n"

	"	ei							\n"

	"1:								\n"

#elif defined(CONFIG_CPU_MIPSR2)

#else

	/*

	 * Fast, dangerous.  Life is fun, life is good.

	 */

	"	mfc0	$1, $12						\n"

	"	ins	$1, \\flags, 0, 1				\n"

	"	mtc0	$1, $12						\n"

#else

	"	mfc0	$1, $12						\n"

	"	andi	\\flags, 1					\n"

	"	ori	$1, 0x1f					\n"

	"	xori	$1, 0x1f					\n"

	"	or	\\flags, $1					\n"

	"	mtc0	\\flags, $12					\n"

#endif

	"	irq_disable_hazard					\n"

	"	.set	pop						\n"

	"	.endm							\n");





static inline void arch_local_irq_restore(unsigned long flags)

{

	unsigned long __tmp1;



#ifdef CONFIG_MIPS_MT_SMTC

	/*

	 * SMTC kernel needs to do a software replay of queued

	 * IPIs, at the cost of branch and call overhead on each

	 * local_irq_restore()

	 */

	if (unlikely(!(flags & 0x0400)))

		smtc_ipi_replay();

#endif



	__asm__ __volatile__(

		"arch_local_irq_restore\t%0"

		: "=r" (__tmp1)
@@ -232,6 +106,75 @@ static inline void __arch_local_irq_restore(unsigned long flags) 
		: "0" (flags)

		: "memory");

}

#else

/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */

void arch_local_irq_disable(void);

unsigned long arch_local_irq_save(void);

void arch_local_irq_restore(unsigned long flags);

void __arch_local_irq_restore(unsigned long flags);

#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */





__asm__(

	"	.macro	arch_local_irq_enable				\n"

	"	.set	push						\n"

	"	.set	reorder						\n"

	"	.set	noat						\n"

#ifdef CONFIG_MIPS_MT_SMTC

	"	mfc0	$1, $2, 1	# SMTC - clear TCStatus.IXMT	\n"

	"	ori	$1, 0x400					\n"

	"	xori	$1, 0x400					\n"

	"	mtc0	$1, $2, 1					\n"

#elif defined(CONFIG_CPU_MIPSR2)

	"	ei							\n"

#else

	"	mfc0	$1,$12						\n"

	"	ori	$1,0x1f						\n"

	"	xori	$1,0x1e						\n"

	"	mtc0	$1,$12						\n"

#endif

	"	irq_enable_hazard					\n"

	"	.set	pop						\n"

	"	.endm");



extern void smtc_ipi_replay(void);



static inline void arch_local_irq_enable(void)

{

#ifdef CONFIG_MIPS_MT_SMTC

	/*

	 * SMTC kernel needs to do a software replay of queued

	 * IPIs, at the cost of call overhead on each local_irq_enable()

	 */

	smtc_ipi_replay();

#endif

	__asm__ __volatile__(

		"arch_local_irq_enable"

		: /* no outputs */

		: /* no inputs */

		: "memory");

}





__asm__(

	"	.macro	arch_local_save_flags flags			\n"

	"	.set	push						\n"

	"	.set	reorder						\n"

#ifdef CONFIG_MIPS_MT_SMTC

	"	mfc0	\\flags, $2, 1					\n"

#else

	"	mfc0	\\flags, $12					\n"

#endif

	"	.set	pop						\n"

	"	.endm							\n");



static inline unsigned long arch_local_save_flags(void)

{

	unsigned long flags;

	asm volatile("arch_local_save_flags %0" : "=r" (flags));

	return flags;

}





static inline int arch_irqs_disabled_flags(unsigned long flags)

{
@@ -245,7 +188,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) 
#endif

}



#endif

#endif /* #ifndef __ASSEMBLY__ */



/*

 * Do the CPU's IRQ-state tracing from assembly code.