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Commit f0c0a54b authored by Taniya Das's avatar Taniya Das
Browse files

clk: msm: Add support for GCC clocks for MDM9x07 



Add snapshot of GCC clock driver for MDM9x07 from msm-3.18
'commit 0dab07645ee3b9a2c ("mm-camera2:isp2: Handle use after free
buffer")'.

Change-Id: I7ca6574d01d02748350509a10fa3e02cac916a9b
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 69737faf

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

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@@ -47,6 +47,8 @@ Required properties: 
			"qcom,gcc-mdss-8920"

			"qcom,gcc-gfx-8953"

			"qcom,gcc-gfx-sdm450"

			"qcom,gcc-mdm9607"

			"qcom,cc-debug-mdm9607"



- reg:                  Pairs of physical base addresses and region sizes of

                        memory mapped registers.

drivers/clk/msm/Makefile

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@@ -20,6 +20,9 @@ obj-$(CONFIG_ARCH_MSM8937) += clock-gcc-8952.o 
obj-$(CONFIG_ARCH_MSM8937)	+= clock-cpu-8939.o

obj-$(CONFIG_ARCH_MSM8937)	+= clock-rcgwr.o

obj-$(CONFIG_ARCH_MSM8953)	+= clock-cpu-sdm632.o



# MDM9607

obj-$(CONFIG_ARCH_MDM9607)      +=clock-gcc-mdm9607.o

endif



obj-y               += mdss/

drivers/clk/msm/clock-gcc-mdm9607.c

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File added.

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include/dt-bindings/clock/mdm-clocks-9607.h

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/*

 * Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef __MDM_CLOCKS_9607_H

#define __MDM_CLOCKS_9607_H



/*PLL Sources */

#define clk_gpll0_clk_src					 0x5933b69f

#define clk_gpll0_ao_clk_src                                     0x6b2fb034

#define clk_gpll2_clk_src					 0x7c34503b

#define clk_gpll1_clk_src					 0x916f8847



#define clk_a7sspll						 0x0b2e5cbd



/*RPM and Voter clocks */

#define clk_pcnoc_clk						 0xc1296d0f

#define clk_pcnoc_a_clk						 0x9bcffee4

#define clk_pcnoc_msmbus_clk					 0x2b53b688

#define clk_pcnoc_msmbus_a_clk					 0x9753a54f

#define clk_pcnoc_keepalive_a_clk				 0x9464f720

#define clk_pcnoc_usb_clk					 0x57adc448

#define clk_pcnoc_usb_a_clk					 0x11d6a74e

#define clk_bimc_clk						 0x4b80bf00

#define clk_bimc_a_clk						 0x4b25668a

#define clk_bimc_msmbus_clk					 0xd212feea

#define clk_bimc_msmbus_a_clk					 0x71d1a499

#define clk_bimc_usb_clk					 0x9bd2b2bf

#define clk_bimc_usb_a_clk					 0xea410834

#define clk_qdss_clk						 0x1492202a

#define clk_qdss_a_clk						 0xdd121669

#define clk_qpic_clk						 0x3ce6f7bb

#define clk_qpic_a_clk						 0xd70ccb7c

#define clk_xo_clk_src						 0x23f5649f

#define clk_xo_a_clk_src					 0x2fdd2c7c

#define clk_xo_otg_clk						 0x79bca5cc

#define clk_xo_lpm_clk						 0x2be48257

#define clk_xo_pil_mss_clk					 0xe97a8354

#define clk_bb_clk1						 0xf5304268

#define clk_bb_clk1_pin						 0x6dd0a779



/* SRCs */

#define clk_apss_ahb_clk_src					 0x36f8495f

#define clk_emac_0_125m_clk_src					 0x955db353

#define clk_blsp1_qup1_i2c_apps_clk_src				 0x17f78f5e

#define clk_blsp1_qup1_spi_apps_clk_src				 0xf534c4fa

#define clk_blsp1_qup2_i2c_apps_clk_src				 0x8de71c79

#define clk_blsp1_qup2_spi_apps_clk_src				 0x33cf809a

#define clk_blsp1_qup3_i2c_apps_clk_src				 0xf161b902

#define clk_blsp1_qup3_spi_apps_clk_src				 0x5e95683f

#define clk_blsp1_qup4_i2c_apps_clk_src				 0xb2ecce68

#define clk_blsp1_qup4_spi_apps_clk_src				 0xddb5bbdb

#define clk_blsp1_qup5_i2c_apps_clk_src				 0x71ea7804

#define clk_blsp1_qup5_spi_apps_clk_src				 0x9752f35f

#define clk_blsp1_qup6_i2c_apps_clk_src				 0x28806803

#define clk_blsp1_qup6_spi_apps_clk_src				 0x44a1edc4

#define clk_blsp1_uart1_apps_clk_src				 0xf8146114

#define clk_blsp1_uart2_apps_clk_src				 0xfc9c2f73

#define clk_blsp1_uart3_apps_clk_src				 0x600497f2

#define clk_blsp1_uart4_apps_clk_src				 0x56bff15c

#define clk_blsp1_uart5_apps_clk_src				 0x218ef697

#define clk_blsp1_uart6_apps_clk_src				 0x8fbdbe4c

#define clk_crypto_clk_src					 0x37a21414

#define clk_gp1_clk_src						 0xad85b97a

#define clk_gp2_clk_src						 0xfb1f0065

#define clk_gp3_clk_src						 0x63b693d6

#define clk_pdm2_clk_src					 0x31e494fd

#define clk_sdcc1_apps_clk_src					 0xd4975db2

#define clk_sdcc2_apps_clk_src					 0xfc46c821

#define clk_emac_0_sys_25m_clk_src				 0x92fe3614

#define clk_emac_0_tx_clk_src					 0x0487ec76

#define clk_usb_hs_system_clk_src				 0x28385546

#define clk_usb_hsic_clk_src					 0x141b01df

#define clk_usb_hsic_io_cal_clk_src				 0xc83584bd

#define clk_usb_hsic_system_clk_src				 0x52ef7224



/*Branch*/

#define clk_gcc_apss_ahb_clk					 0x2b0d39ff

#define clk_gcc_apss_axi_clk					 0x1d47f4ff

#define clk_gcc_prng_ahb_clk					 0x397e7eaa

#define clk_gcc_qdss_dap_clk					 0x7fa9aa73

#define clk_gcc_apss_tcu_clk					 0xaf56a329

#define clk_gcc_blsp1_ahb_clk					 0x8caa5b4f

#define clk_gcc_blsp1_qup1_i2c_apps_clk				 0xc303fae9

#define clk_gcc_blsp1_qup1_spi_apps_clk				 0x759a76b0

#define clk_gcc_blsp1_qup2_i2c_apps_clk				 0x1076f220

#define clk_gcc_blsp1_qup2_spi_apps_clk				 0x3e77d48f

#define clk_gcc_blsp1_qup3_i2c_apps_clk				 0x9e25ac82

#define clk_gcc_blsp1_qup3_spi_apps_clk				 0xfb978880

#define clk_gcc_blsp1_qup4_i2c_apps_clk				 0xd7f40f6f

#define clk_gcc_blsp1_qup4_spi_apps_clk				 0x80f8722f

#define clk_gcc_blsp1_qup5_i2c_apps_clk				 0xacae5604

#define clk_gcc_blsp1_qup5_spi_apps_clk				 0xbf3e15d7

#define clk_gcc_blsp1_qup6_i2c_apps_clk				 0x5c6ad820

#define clk_gcc_blsp1_qup6_spi_apps_clk				 0x780d9f85

#define clk_gcc_blsp1_uart1_apps_clk				 0xc7c62f90

#define clk_gcc_blsp1_uart2_apps_clk				 0xf8a61c96

#define clk_gcc_blsp1_uart3_apps_clk				 0xc3298bd7

#define clk_gcc_blsp1_uart4_apps_clk				 0x26be16c0

#define clk_gcc_blsp1_uart5_apps_clk				 0x28a6bc74

#define clk_gcc_blsp1_uart6_apps_clk				 0x28fd3466

#define clk_gcc_boot_rom_ahb_clk				 0xde2adeb1

#define clk_gcc_crypto_ahb_clk					 0x94de4919

#define clk_gcc_crypto_axi_clk					 0xd4415c9b

#define clk_gcc_crypto_clk					 0x00d390d2

#define clk_gcc_gp1_clk						 0x057f7b69

#define clk_gcc_gp2_clk						 0x9bf83ffd

#define clk_gcc_gp3_clk						 0xec6539ee

#define clk_gcc_mss_cfg_ahb_clk					 0x111cde81

#define clk_gcc_mss_q6_bimc_axi_clk				 0x67544d62

#define clk_gcc_pdm2_clk					 0x99d55711

#define clk_gcc_pdm_ahb_clk					 0x365664f6

#define clk_gcc_sdcc1_ahb_clk					 0x691e0caa

#define clk_gcc_sdcc1_apps_clk					 0x9ad6fb96

#define clk_gcc_sdcc2_ahb_clk					 0x23d5727f

#define clk_gcc_sdcc2_apps_clk					 0x861b20ac

#define clk_gcc_emac_0_125m_clk					 0xe556de53

#define clk_gcc_emac_0_ahb_clk					 0x6a741d38

#define clk_gcc_emac_0_axi_clk					 0xf2b04fb4

#define clk_gcc_emac_0_rx_clk					 0x869a4e5c

#define clk_gcc_emac_0_sys_25m_clk				 0x5812832b

#define clk_gcc_emac_0_sys_clk					 0x34fb62b0

#define clk_gcc_emac_0_tx_clk					 0x331d3573

#define clk_gcc_smmu_cfg_clk					 0x75eaefa5

#define clk_gcc_usb2a_phy_sleep_clk				 0x6caa736f

#define clk_gcc_usb_hs_phy_cfg_ahb_clk				 0xe13808fd

#define clk_gcc_usb_hs_ahb_clk					 0x72ce8032

#define clk_gcc_usb_hs_system_clk				 0xa11972e5

#define clk_gcc_usb_hsic_ahb_clk				 0x3ec2631a

#define clk_gcc_usb_hsic_clk					 0x8de18b0e

#define clk_gcc_usb_hsic_io_cal_clk				 0xbc21f776

#define clk_gcc_usb_hsic_io_cal_sleep_clk			 0x20e09a22

#define clk_gcc_usb_hsic_system_clk				 0x145e9366

#define clk_gcc_usb2_hs_phy_only_clk				 0x0047179d

#define clk_gcc_qusb2_phy_clk					 0x996884d5

/* DEBUG */

#define clk_gcc_debug_mux					 0x8121ac15

#define clk_apss_debug_pri_mux					 0xc691ff55

#define clk_apc0_m_clk						 0xce1e9473

#define clk_apc1_m_clk						 0x990fbaf7

#define clk_apc2_m_clk						 0x252cd4ae

#define clk_apc3_m_clk						 0x78c64486

#define clk_l2_m_clk						 0x4bedf4d0



#define clk_wcnss_m_clk						 0x709f430b



#endif

include/dt-bindings/clock/mdm-clocks-hwio-9607.h

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/*

 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef __MDM_CLOCKS_9607_HWIO_H

#define __MDM_CLOCKS_9607_HWIO_H



#define GPLL0_MODE				0x21000

#define GPLL0_STATUS				0x21024

#define GPLL1_MODE				0x20000

#define GPLL1_STATUS				0x2001C

#define GPLL2_MODE				0x25000

#define GPLL2_STATUS				0x25024

#define APCS_GPLL_ENA_VOTE			0x45000

#define APCS_MODE				0x00018

#define APSS_AHB_CMD_RCGR			0x46000

#define PRNG_AHB_CBCR				0x13004

#define EMAC_0_125M_CMD_RCGR			0x4E028

#define BLSP1_QUP1_I2C_APPS_CMD_RCGR		 0x200C

#define BLSP1_QUP1_SPI_APPS_CMD_RCGR		 0x2024

#define BLSP1_QUP2_I2C_APPS_CMD_RCGR		 0x3000

#define BLSP1_QUP2_SPI_APPS_CMD_RCGR		 0x3014

#define BLSP1_QUP3_I2C_APPS_CMD_RCGR		 0x4000

#define BLSP1_QUP3_SPI_APPS_CMD_RCGR		 0x4024

#define BLSP1_QUP4_I2C_APPS_CMD_RCGR		 0x5000

#define BLSP1_QUP4_SPI_APPS_CMD_RCGR		 0x5024

#define BLSP1_QUP5_I2C_APPS_CMD_RCGR		 0x6000

#define BLSP1_QUP5_SPI_APPS_CMD_RCGR		 0x6024

#define BLSP1_QUP6_I2C_APPS_CMD_RCGR		 0x7000

#define BLSP1_QUP6_SPI_APPS_CMD_RCGR		 0x7024

#define BLSP1_UART1_APPS_CMD_RCGR		 0x2044

#define BLSP1_UART2_APPS_CMD_RCGR		 0x3034

#define BLSP1_UART3_APPS_CMD_RCGR		 0x4044

#define BLSP1_UART4_APPS_CMD_RCGR		 0x5044

#define BLSP1_UART5_APPS_CMD_RCGR		 0x6044

#define BLSP1_UART6_APPS_CMD_RCGR		 0x7044

#define CRYPTO_CMD_RCGR			0x16004

#define GP1_CMD_RCGR				 0x8004

#define GP2_CMD_RCGR				 0x9004

#define GP3_CMD_RCGR				 0xA004

#define PDM2_CMD_RCGR				0x44010

#define QPIC_CMD_RCGR				0x3F004

#define SDCC1_APPS_CMD_RCGR			0x42004

#define SDCC2_APPS_CMD_RCGR			0x43004

#define EMAC_0_SYS_25M_CMD_RCGR		0x4E03C

#define EMAC_0_TX_CMD_RCGR			0x4E014

#define USB_HS_SYSTEM_CMD_RCGR			0x41010

#define USB_HSIC_CMD_RCGR			0x3D018

#define USB_HSIC_IO_CAL_CMD_RCGR		0x3D030

#define USB_HSIC_SYSTEM_CMD_RCGR		0x3D000

#define BIMC_PCNOC_AXI_CBCR			0x31024

#define BLSP1_AHB_CBCR				 0x1008

#define APCS_CLOCK_BRANCH_ENA_VOTE		0x45004

#define BLSP1_QUP1_I2C_APPS_CBCR		 0x2008

#define BLSP1_QUP1_SPI_APPS_CBCR		 0x2004

#define BLSP1_QUP2_I2C_APPS_CBCR		 0x3010

#define BLSP1_QUP2_SPI_APPS_CBCR		 0x300C

#define BLSP1_QUP3_I2C_APPS_CBCR		 0x4020

#define BLSP1_QUP3_SPI_APPS_CBCR		 0x401C

#define BLSP1_QUP4_I2C_APPS_CBCR		 0x5020

#define BLSP1_QUP4_SPI_APPS_CBCR		 0x501C

#define BLSP1_QUP5_I2C_APPS_CBCR		 0x6020

#define BLSP1_QUP5_SPI_APPS_CBCR		 0x601C

#define BLSP1_QUP6_I2C_APPS_CBCR		 0x7020

#define BLSP1_QUP6_SPI_APPS_CBCR		 0x701C

#define BLSP1_UART1_APPS_CBCR			 0x203C

#define BLSP1_UART2_APPS_CBCR			 0x302C

#define BLSP1_UART3_APPS_CBCR			 0x403C

#define BLSP1_UART4_APPS_CBCR			 0x503C

#define BLSP1_UART5_APPS_CBCR			 0x603C

#define BLSP1_UART6_APPS_CBCR			 0x703C

#define APSS_AHB_CBCR				0x4601C

#define APSS_AXI_CBCR				0x46020

#define BOOT_ROM_AHB_CBCR			0x1300C

#define CRYPTO_AHB_CBCR			0x16024

#define CRYPTO_AXI_CBCR			0x16020

#define CRYPTO_CBCR				0x1601C

#define GP1_CBCR				 0x8000

#define GP2_CBCR				 0x9000

#define GP3_CBCR				 0xA000

#define MSS_CFG_AHB_CBCR			0x49000

#define MSS_Q6_BIMC_AXI_CBCR			0x49004

#define PCNOC_APSS_AHB_CBCR			0x27030

#define PDM2_CBCR				0x4400C

#define PDM_AHB_CBCR				0x44004

#define QPIC_AHB_CBCR				0x3F01C

#define QPIC_CBCR				0x3F018

#define QPIC_SYSTEM_CBCR			0x3F020

#define SDCC1_AHB_CBCR				0x4201C

#define SDCC1_APPS_CBCR			0x42018

#define SDCC2_AHB_CBCR				0x4301C

#define SDCC2_APPS_CBCR			0x43018

#define EMAC_0_125M_CBCR			0x4E010

#define EMAC_0_AHB_CBCR			0x4E000

#define EMAC_0_AXI_CBCR			0x4E008

#define EMAC_0_RX_CBCR				0x4E030

#define EMAC_0_SYS_25M_CBCR			0x4E038

#define EMAC_0_SYS_CBCR				0x4E034

#define EMAC_0_TX_CBCR				0x4E00C

#define APSS_TCU_CBCR				0x12018

#define SMMU_CFG_CBCR				0x12038

#define QDSS_DAP_CBCR				0x29084

#define APCS_SMMU_CLOCK_BRANCH_ENA_VOTE		0x4500C

#define USB2A_PHY_SLEEP_CBCR			0x4102C

#define USB_HS_PHY_CFG_AHB_CBCR			0x41030

#define USB_HS_AHB_CBCR				0x41008

#define USB_HS_SYSTEM_CBCR			0x41004

#define USB_HS_BCR				0x41000

#define USB_HSIC_AHB_CBCR			0x3D04C

#define USB_HSIC_CBCR				0x3D050

#define USB_HSIC_IO_CAL_CBCR			0x3D054

#define USB_HSIC_IO_CAL_SLEEP_CBCR		0x3D058

#define USB_HSIC_SYSTEM_CBCR			0x3D048

#define USB_HS_HSIC_BCR				0x3D05C

#define USB2_HS_PHY_ONLY_BCR			0x41034

#define QUSB2_PHY_BCR				0x4103C

#define GCC_DEBUG_CLK_CTL			0x74000

#define CLOCK_FRQ_MEASURE_CTL			0x74004

#define CLOCK_FRQ_MEASURE_STATUS		0x74008

#define PLLTEST_PAD_CFG			0x7400C

#define GCC_XO_DIV4_CBCR			0x30034



#define xo_source_val				0

#define xo_a_source_val			0

#define gpll0_source_val			1

#define gpll2_source_val			1

#define emac_0_125m_clk_source_val		1

#define emac_0_tx_clk_source_val		2



#define F(f, s, div, m, n) \

	{ \

		.freq_hz = (f), \

		.src_clk = &s##_clk_src.c, \

		.m_val = (m), \

		.n_val = ~((n)-(m)) * !!(n), \

		.d_val = ~(n),\

		.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \

			| BVAL(10, 8, s##_source_val), \

	}



#define F_EXT(f, s, div, m, n) \

	{ \

		.freq_hz = (f), \

		.m_val = (m), \

		.n_val = ~((n)-(m)) * !!(n), \

		.d_val = ~(n),\

		.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \

			| BVAL(10, 8, s##_source_val), \

		}



#define VDD_DIG_FMAX_MAP1(l1, f1) \

	.vdd_class = &vdd_dig, \

	.fmax = (unsigned long[VDD_DIG_NUM]) {  \

		[VDD_DIG_##l1] = (f1),          \

	},                                      \

	.num_fmax = VDD_DIG_NUM



#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \

	.vdd_class = &vdd_dig, \

	.fmax = (unsigned long[VDD_DIG_NUM]) {  \

		[VDD_DIG_##l1] = (f1),          \

		[VDD_DIG_##l2] = (f2),          \

	},                                      \

	.num_fmax = VDD_DIG_NUM



#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \

	.vdd_class = &vdd_dig, \

	.fmax = (unsigned long[VDD_DIG_NUM]) {  \

		[VDD_DIG_##l1] = (f1),          \

		[VDD_DIG_##l2] = (f2),          \

		[VDD_DIG_##l3] = (f3),          \

	},                                      \

	.num_fmax = VDD_DIG_NUM



enum vdd_dig_levels {

	VDD_DIG_NONE,

	VDD_DIG_LOWER,

	VDD_DIG_LOW,

	VDD_DIG_NOMINAL,

	VDD_DIG_HIGH,

	VDD_DIG_NUM

};



static int vdd_corner[] = {

	RPM_REGULATOR_LEVEL_NONE,              /* VDD_DIG_NONE */

	RPM_REGULATOR_LEVEL_SVS,		/* VDD_DIG_LOWER */

	RPM_REGULATOR_LEVEL_SVS_PLUS,		/*VDD_DIG_LOW*/

	RPM_REGULATOR_LEVEL_NOM,            /* VDD_DIG_NOMINAL */

	RPM_REGULATOR_LEVEL_TURBO,		/* VDD_DIG_HIGH */

};



static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);





#define VDD_STROMER_FMAX_MAP1(l1, f1) \

	.vdd_class = &vdd_stromer_pll, \

	.fmax = (unsigned long[VDD_DIG_NUM]) {  \

		[VDD_DIG_##l1] = (f1),          \

	},                                      \

	.num_fmax = VDD_DIG_NUM





#define RPM_MISC_CLK_TYPE			0x306b6c63

#define RPM_BUS_CLK_TYPE			0x316b6c63

#define RPM_MEM_CLK_TYPE			0x326b6c63

#define RPM_SMD_KEY_ENABLE			0x62616E45

#define RPM_QPIC_CLK_TYPE			0x63697071



#define XO_ID					0x0

#define QDSS_ID				0x1

#define PCNOC_ID				0x0

#define BIMC_ID				0x0

#define QPIC_ID				0x0



/* XO clock */

#define BB_CLK1_ID				1

#define RF_CLK2_ID				5



#endif