Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f03cbea3 authored by Hartmut Hackmann's avatar Hartmut Hackmann Committed by Linus Torvalds
Browse files

[PATCH] dvb: frontend: tda1004x: support tda827x tuners



o added preliminary support for tda827x tuners
o set parameters for drift compensation to 0
  makes no sense for DVB-T but can prevent lock

Signed-off-by: default avatarHartmut Hackmann <hartmut.hackmann@t-online.de>
Signed-off-by: default avatarJohannes Stezenbach <js@linuxtv.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 0c744b01
Loading
Loading
Loading
Loading
+40 −4
Original line number Diff line number Diff line
@@ -120,6 +120,8 @@ static int debug;
#define TDA10046H_GPIO_OUT_SEL	 0x41
#define TDA10046H_GPIO_SELECT	 0x42
#define TDA10046H_AGC_CONF	 0x43
#define TDA10046H_AGC_THR	 0x44
#define TDA10046H_AGC_RENORM	 0x45
#define TDA10046H_AGC_GAINS	 0x46
#define TDA10046H_AGC_TUN_MIN	 0x47
#define TDA10046H_AGC_TUN_MAX	 0x48
@@ -272,14 +274,26 @@ static int tda10046h_set_bandwidth(struct tda1004x_state *state,
	switch (bandwidth) {
	case BANDWIDTH_6_MHZ:
		tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
		if (state->config->if_freq == TDA10046_FREQ_045) {
			tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x09);
			tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x4f);
		}
		break;

	case BANDWIDTH_7_MHZ:
		tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
		if (state->config->if_freq == TDA10046_FREQ_045) {
			tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
			tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x79);
		}
		break;

	case BANDWIDTH_8_MHZ:
		tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
		if (state->config->if_freq == TDA10046_FREQ_045) {
			tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b);
			tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3);
		}
		break;

	default:
@@ -420,6 +434,14 @@ static void tda10046_init_plls(struct dvb_frontend* fe)
		tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
		tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13);
		break;
	case TDA10046_FREQ_045:
		tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b);
		tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3);
		break;
	case TDA10046_FREQ_052:
		tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
		tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x06);
		break;
	}
	tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
}
@@ -590,6 +612,16 @@ static int tda10046_init(struct dvb_frontend* fe)
		tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
		tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
		break;
	case TDA10046_AGC_IFO_AUTO_POS:
		tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
		tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities
		break;
	case TDA10046_AGC_TDA827X:
		tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
		tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
		tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x0E); // Gain Renormalize
		tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
		break;
	}
	tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
	tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);	  // }
@@ -1091,9 +1123,12 @@ static int tda1004x_sleep(struct dvb_frontend* fe)
		break;

	case TDA1004X_DEMOD_TDA10046:
		tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
		if (state->config->pll_sleep != NULL)
		if (state->config->pll_sleep != NULL) {
			tda1004x_enable_tuner_i2c(state);
			state->config->pll_sleep(fe);
			tda1004x_disable_tuner_i2c(state);
		}
		tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
		break;
	}
	state->initialised = 0;
@@ -1104,8 +1139,9 @@ static int tda1004x_sleep(struct dvb_frontend* fe)
static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
{
	fesettings->min_delay_ms = 800;
	fesettings->step_size = 166667;
	fesettings->max_drift = 166667*2;
	/* Drift compensation makes no sense for DVB-T */
	fesettings->step_size = 0;
	fesettings->max_drift = 0;
	return 0;
}

+4 −0
Original line number Diff line number Diff line
@@ -34,11 +34,15 @@ enum tda10046_xtal {
enum tda10046_agc {
	TDA10046_AGC_DEFAULT,		/* original configuration */
	TDA10046_AGC_IFO_AUTO_NEG,	/* IF AGC only, automatic, negtive */
	TDA10046_AGC_IFO_AUTO_POS,	/* IF AGC only, automatic, positive */
	TDA10046_AGC_TDA827X,	    /* IF AGC only, special setup for tda827x */
};

enum tda10046_if {
	TDA10046_FREQ_3617,		/* original config, 36,166 MHZ */
	TDA10046_FREQ_3613,		/* 36,13 MHZ */
	TDA10046_FREQ_045,		/* low IF, 4.0, 4.5, or 5.0 MHZ */
	TDA10046_FREQ_052,		/* low IF, 5.1667 MHZ for tda9889 */
};

struct tda1004x_config