Commit efd87da6 authored Jun 05, 2017 by Vicky Wallace

clk: qcom: clk-alpha-pll: Update round rate to use kHz for the divider



For the PLL that have 32 bits support for the division ratio.
The DIVIDER_ROUND_CLOSEST flag is designed to round the frequency
to the closest Hz for the requested rate.
However the Fabia PLLs have only 16 bits support for the
division ratio. Using the closest rounding flag results in
a parent PLL being configured with the rate larger than Fmax.
This change solves the issue by allowing the frequency to round
to nearest kHz.

CRs-Fixed: 2048646
Change-Id: I336945df289e383dea2b831ec8aa24da2aca54c1
Signed-off-by: Vicky Wallace <vwallace@codeaurora.org>

parent e13b3810

drivers/clk/qcom/clk-alpha-pll.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -815,7 +815,7 @@ static long clk_generic_pll_postdiv_round_rate(struct clk_hw *hw,
		return -EINVAL;

		return divider_round_rate(hw, rate, prate, pll->post_div_table,
		pll->width, CLK_DIVIDER_ROUND_CLOSEST);
		pll->width, CLK_DIVIDER_ROUND_KHZ);
		}

		static int clk_generic_pll_postdiv_set_rate(struct clk_hw *hw,