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Commit ef909d67 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Liam Girdwood
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ASoC: tlv320dac33: Optimize power up, and restore 



On power up we only need to initialize the codec, and
restore only registers, which are not in either in DAPM
nor in the playback start sequence.
These are mostly gain related registers.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: default avatarLiam Girdwood <lrg@slimlogic.co.uk>
parent 1b7c9afb

sound/soc/codecs/tlv320dac33.c

+39 −67
Original line number Original line Diff line number Diff line
@@ -284,45 +284,49 @@ static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg, 
	return ret;

	return ret;

}

}





static void dac33_restore_regs(struct snd_soc_codec *codec)

static void dac33_init_chip(struct snd_soc_codec *codec)

{

{

	struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);

	struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);

	u8 *cache = codec->reg_cache;

	u8 data[2];

	int i, ret;





	if (!dac33->chip_power)

	if (unlikely(!dac33->chip_power))

		return;

		return;





	for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {

	/* 44-46: DAC Control Registers */

		data[0] = i;

	/* A : DAC sample rate Fsref/1.5 */

		data[1] = cache[i];

	dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));

		/* Skip the read only registers */

	/* B : DAC src=normal, not muted */

		if ((i >= DAC33_INT_OSC_STATUS &&

	dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |

				i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||

					     DAC33_DACSRCL_LEFT);

		    (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||

	/* C : (defaults) */

		    i == DAC33_DAC_STATUS_FLAGS ||

	dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);

		    i == DAC33_SRC_EST_REF_CLK_RATIO_A ||



		    i == DAC33_SRC_EST_REF_CLK_RATIO_B)

	/* 64-65 : L&R DAC power control

			continue;

	 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/

		ret = codec->hw_write(codec->control_data, data, 2);

	dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));

		if (ret != 2)

	dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));

			dev_err(codec->dev, "Write failed (%d)\n", ret);



	}

	/* 73 : volume soft stepping control,

	for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {

	 clock source = internal osc (?) */

		data[0] = i;

	dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);

		data[1] = cache[i];



		ret = codec->hw_write(codec->control_data, data, 2);

	/* 66 : LOP/LOM Modes */

		if (ret != 2)

	dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);

			dev_err(codec->dev, "Write failed (%d)\n", ret);



	}

	/* 68 : LOM inverted from LOP */

	for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {

	dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));

		data[0] = i;



		data[1] = cache[i];

	dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);

		ret = codec->hw_write(codec->control_data, data, 2);



		if (ret != 2)

	/* Restore only selected registers (gains mostly) */

			dev_err(codec->dev, "Write failed (%d)\n", ret);

	dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,

	}

		    dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));

	dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,

		    dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));



	dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,

		    dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));

	dac33_write(codec, DAC33_LINER_TO_RLO_VOL,

		    dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));

}

}





static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)

static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
@@ -358,8 +362,7 @@ static int dac33_hard_power(struct snd_soc_codec *codec, int power) 




		dac33->chip_power = 1;

		dac33->chip_power = 1;





		/* Restore registers */

		dac33_init_chip(codec);

		dac33_restore_regs(codec);





		dac33_soft_power(codec, 1);

		dac33_soft_power(codec, 1);

	} else {

	} else {
@@ -1269,35 +1272,6 @@ static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, 
	return 0;

	return 0;

}

}





static void dac33_init_chip(struct snd_soc_codec *codec)

{

	/* 44-46: DAC Control Registers */

	/* A : DAC sample rate Fsref/1.5 */

	dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));

	/* B : DAC src=normal, not muted */

	dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |

					     DAC33_DACSRCL_LEFT);

	/* C : (defaults) */

	dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);



	/* 64-65 : L&R DAC power control

	 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/

	dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));

	dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));



	/* 73 : volume soft stepping control,

	 clock source = internal osc (?) */

	dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);



	/* 66 : LOP/LOM Modes */

	dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);



	/* 68 : LOM inverted from LOP */

	dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));



	dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);

}



static int dac33_soc_probe(struct platform_device *pdev)

static int dac33_soc_probe(struct platform_device *pdev)

{

{

	struct snd_soc_device *socdev = platform_get_drvdata(pdev);

	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
@@ -1313,8 +1287,6 @@ static int dac33_soc_probe(struct platform_device *pdev) 




	/* Power up the codec */

	/* Power up the codec */

	dac33_hard_power(codec, 1);

	dac33_hard_power(codec, 1);

	/* Set default configuration */

	dac33_init_chip(codec);





	/* register pcms */

	/* register pcms */

	ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);

	ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);